MAX® 10 Analog to Digital Converter User Guide

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ID 683596
Date 3/10/2025
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Document Table of Contents
Document Table of Contents x
1. MAX® 10 Analog to Digital Converter Overview 2. MAX® 10 ADC Architecture and Features 3. MAX® 10 ADC Design Considerations 4. MAX® 10 ADC Implementation Guides 5. Modular ADC Core Intel® FPGA IP and Modular Dual ADC Core Intel® FPGA IP References 6. MAX® 10 Analog to Digital Converter User Guide Archives 7. Document Revision History for the MAX® 10 Analog to Digital Converter User Guide
1. MAX® 10 Analog to Digital Converter Overview x
1.1. ADC Block Counts in MAX® 10 Devices 1.2. ADC Channel Counts in MAX® 10 Devices 1.3. MAX® 10 ADC Vertical Migration Support 1.4. MAX® 10 Single or Dual Supply Devices 1.5. MAX® 10 ADC Conversion
1.5. MAX® 10 ADC Conversion x
1.5.1. Voltage Representation Conversion
2. MAX® 10 ADC Architecture and Features x
2.1. MAX® 10 ADC Hard IP Block 2.2. Modular ADC Core and Modular Dual ADC Core IP Cores 2.3. Altera® FPGA ADC HAL Driver 2.4. ADC Toolkit for Testing ADC Performance 2.5. ADC Logic Simulation Output
2.1. MAX® 10 ADC Hard IP Block x
2.1.1. ADC Block Locations 2.1.2. Single or Dual ADC Devices 2.1.3. ADC Analog Input Pins 2.1.4. ADC Prescaler 2.1.5. ADC Clock Sources 2.1.6. ADC Voltage Reference 2.1.7. ADC Temperature Sensing Diode 2.1.8. ADC Sequencer 2.1.9. ADC Timing
2.1.7. ADC Temperature Sensing Diode x
2.1.7.1. Temperature Measurement Code Conversion 2.1.7.2. Temperature Measurement Sampling Rate
2.1.8. ADC Sequencer x
2.1.8.1. Guidelines: ADC Sequencer in Modular Dual ADC Core IP Core
2.2. Modular ADC Core and Modular Dual ADC Core IP Cores x
2.2.1. Modular ADC Core IP Core Configuration Variants 2.2.2. Modular ADC Core and Modular Dual ADC Core IP Cores Architecture
2.2.1. Modular ADC Core IP Core Configuration Variants x
2.2.1.1. Configuration 1: Standard Sequencer with Avalon-MM Sample Storage 2.2.1.2. Configuration 2: Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation Detection 2.2.1.3. Configuration 3: Standard Sequencer with External Sample Storage 2.2.1.4. Configuration 4: ADC Control Core Only
2.2.2. Modular ADC Core and Modular Dual ADC Core IP Cores Architecture x
2.2.2.1. ADC Control Core 2.2.2.2. Sequencer Core 2.2.2.3. Sample Storage Core 2.2.2.4. Response Merge Core 2.2.2.5. Dual ADC Synchronizer Core 2.2.2.6. Threshold Detection Core
2.5. ADC Logic Simulation Output x
2.5.1. Fixed ADC Logic Simulation Output 2.5.2. User-Specified ADC Logic Simulation Output
3. MAX® 10 ADC Design Considerations x
3.1. Guidelines: ADC Ground Plane Connection 3.2. Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND) 3.3. Guidelines: Board Design for Analog Input 3.4. Guidelines: Board Design for ADC Reference Voltage Pin
4. MAX® 10 ADC Implementation Guides x
4.1. Creating MAX® 10 ADC Design 4.2. Customizing and Generating Modular ADC Core IP Core 4.3. Parameters Settings for Generating ALTPLL IP Core 4.4. Parameters Settings for Generating Modular ADC Core or Modular Dual ADC Core IP Core 4.5. Completing ADC Design
5. Modular ADC Core Intel® FPGA IP and Modular Dual ADC Core Intel® FPGA IP References x
5.1. Modular ADC Core Parameters Settings 5.2. Modular Dual ADC Core Parameters Settings 5.3. Valid ADC Sample Rate and Input Clock Combination 5.4. Modular ADC Core and Modular Dual ADC Core Interface Signals 5.5. Modular ADC Core Register Definitions 5.6. ADC HAL Device Driver for Nios® Processor
5.1. Modular ADC Core Parameters Settings x
5.1.1. Modular ADC Core IP Core Channel Name to MAX® 10 Device Pin Name Mapping
5.2. Modular Dual ADC Core Parameters Settings x
5.2.1. Modular Dual ADC Core IP Core Channel Name to MAX® 10 Device Pin Name Mapping
5.4. Modular ADC Core and Modular Dual ADC Core Interface Signals x
5.4.1. Command Interface of Modular ADC Core and Modular Dual ADC Core 5.4.2. Response Interface of Modular ADC Core and Modular Dual ADC Core 5.4.3. Threshold Interface of Modular ADC Core and Modular Dual ADC Core 5.4.4. CSR Interface of Modular ADC Core and Modular Dual ADC Core 5.4.5. IRQ Interface of Modular ADC Core and Modular Dual ADC Core 5.4.6. Peripheral Clock Interface of Modular ADC Core and Modular Dual ADC Core 5.4.7. Peripheral Reset Interface of Modular ADC Core and Modular Dual ADC Core 5.4.8. ADC PLL Clock Interface of Modular ADC Core and Modular Dual ADC Core 5.4.9. ADC PLL Locked Interface of Modular ADC Core and Modular Dual ADC Core
5.5. Modular ADC Core Register Definitions x
5.5.1. Sequencer Core Registers 5.5.2. Sample Storage Core Registers
5.6. ADC HAL Device Driver for Nios® Processor x
5.6.1. Driver API
1. MAX® 10 Analog to Digital Converter Overview
2. MAX® 10 ADC Architecture and Features
3. MAX® 10 ADC Design Considerations
4. MAX® 10 ADC Implementation Guides
5. Modular ADC Core Intel® FPGA IP and Modular Dual ADC Core Intel® FPGA IP References
6. MAX® 10 Analog to Digital Converter User Guide Archives
7. Document Revision History for the MAX® 10 Analog to Digital Converter User Guide

5.6.1. Driver API

Table 40.  adc_stop
Prototype: void adc_stop(int sequencer_base)
Include:
  • altera_modular_adc.h
  • altera_modular_dual_adc.h
Parameter:
  • sequencer_base – Sequencer base value
Return: -
Description: Writes 0 to the Sequencer CMD register RUN bit, and polls the RUN bit until it is 0.
Table 41.  adc_start
Prototype: void adc_start(int sequencer_base)
Include:
  • altera_modular_adc.h
  • altera_modular_dual_adc.h
Parameter:
  • sequencer_base – Sequencer base value
Return: -
Description: Writes 1 to the Sequencer CMD register RUN bit.
Table 42.  adc_set_mode_run_once
Prototype: void adc_set_mode_run_once(int sequencer_base)
Include:
  • altera_modular_adc.h
  • altera_modular_dual_adc.h
Parameter:
  • sequencer_base – Sequencer base value
Return: -
Description:

Writes 1 to the Sequencer CMD register MODE bit once.

Note: Stop the ADC before calling this function. While RUN bit is set, changing ADC mode has no effect.

Table 43.  adc_set_mode_run_continuously
Prototype: void adc_set_mode_run_continuously(int sequencer_base)
Include:
  • altera_modular_adc.h
  • altera_modular_dual_adc.h
Parameter:
  • sequencer_base – Sequencer base value
Return: -
Description:

Writes 1 to the Sequencer CMD register MODE bit to continuous.

Note: Stop the ADC before calling this function. While RUN bit is set, changing ADC mode has no effect.

Table 44.  adc_recalibrate
Prototype: void adc_recalibrate(int sequencer_base)
Include:
  • altera_modular_adc.h
  • altera_modular_dual_adc.h
Parameter:
  • sequencer_base – Sequencer base value
Return: -
Description:

The function performs as follows,

  1. Backup Sequencer CMD register (because some values can be overwritten).
  2. Stop the ADC Sequencer Core.
  3. Set the recalibration request bits.
  4. Start the ADC Sequencer Core.
  5. Poll for RUN bit to be clear.
  6. Restore Sequencer CMD register
Table 45.  adc_interrupt_enable
Prototype: void adc_interrupt_enable(int sample_store_base)
Include:
  • altera_modular_adc.h
  • altera_modular_dual_adc.h
Parameter:
  • sample_store_base – Base address of sample store core
Return: -
Description: Sets the M_EOP bit in the ADC Sample Storage IER register.
Table 46.  adc_interrupt_disable
Prototype: void adc_interrupt_disable(int sample_store_base)
Include:
  • altera_modular_adc.h
  • altera_modular_dual_adc.h
Parameter:
  • sample_store_base – Base address of sample store core
Return: -
Description: Clears the M_EOP bit in the ADC Sample Storage IER register.
Table 47.  adc_clear_interrupt_status
Prototype: void adc_clear_interrupt_status(int sample_store_base)
Include:
  • altera_modular_adc.h
  • altera_modular_dual_adc.h
Parameter:
  • sample_store_base – Base address of sample store core
Return: -
Description: Clears the EOP bits in the Sample Storage ISR register.
Table 48.  adc_wait_for_interrupt
Prototype: void adc_wait_for_interrupt(int sample_store_base)
Include:
  • altera_modular_adc.h
  • altera_modular_dual_adc.h
Parameter:
  • sample_store_base – Base address of sample store core
Return: -
Description: Waits while the EOP bit of Sample Storage ISR register is 0.
Table 49.  adc_interrupt_asserted
Prototype: int adc_interrupt_asserted(int sample_store_base)
Include:
  • altera_modular_adc.h
  • altera_modular_dual_adc.h
Parameter:
  • sample_store_base – Base address of sample store core
Return: Return -1 if EOP bit is set, 0 if otherwise
Description: Reads the EOP bit of Sample Storage IRQ ISR register.
Table 50.  alt_adc_word_read
Prototype: void alt_adc_word_read(alt_u32 sample_store_base, alt_u32* dest_ptr, alt_u32 len)
Include:
  • altera_modular_adc.h
  • altera_modular_dual_adc.h
Parameter:
  • sample_store_base – Base address of sample store core
  • dest_ptr – destination buffer
  • len – number of 32-bit reads
Return: -
Description: Reads words from the sample store.

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