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2.1. Installation and Licensing
2.2. Generating a CPRI IP
2.3. CPRI IP Parameters
2.4. Integrating the CPRI IP into your Design: Required External Blocks
2.5. Simulating Intel FPGA IP Cores
2.6. Running the CPRI IP Design Example
2.7. CPRI IP Design Example Clocks
2.8. About the Testbench
2.9. Compiling the Full Design and Programming the FPGA
2.4.1. Adding the Transceiver TX PLL IP
2.4.2. Adding the Reset Controller
2.4.3. Adding the Transceiver Reconfiguration Controller
2.4.4. Adding the Off-Chip Clean-Up PLL
2.4.5. Adding and Connecting the Single-Trip Delay Calibration Blocks
2.4.6. CPRI IP Transceiver PLL Calibration
2.4.7. Reference and System PLL Clock for your IP Design
3.1. Interfaces Overview
3.2. CPRI IP Clocking Structure
3.3. CPRI IP Reset Requirements
3.4. Start-Up Sequence Following Reset
3.5. AUX Interface
3.6. Direct IQ Interface
3.7. Ctrl_AxC Interface
3.8. Direct Vendor Specific Access Interface
3.9. Real-Time Vendor Specific Interface
3.10. Direct HDLC Serial Interface
3.11. Direct L1 Control and Status Interface
3.12. L1 Debug Interface
3.13. Media Independent Interface (MII) to External Ethernet Block
3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block
3.15. CPU Interface to CPRI IP Registers
3.16. Auto-Rate Negotiation
3.17. Extended Delay Measurement
3.18. CPRI IP Deterministic Latency
3.19. CPRI IP Transceiver and Transceiver Management Interfaces
3.20. Testing Features
3.19.1. CPRI Link
3.19.2. Main Transceiver Clock and Reset Signals
3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface
3.19.4. Arria® 10, Stratix® 10, and Agilex® 7 Transceiver Reconfiguration Interface
3.19.5. RS-FEC Interface
3.19.6. Interface to the External Reset Controller
3.19.7. Interface to the External PLL
3.19.8. Transceiver Debug Interface
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1. About the CPRI IP
Updated for: |
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Intel® Quartus® Prime Design Suite 25.1 |
IP Version 19.10.0 |
The Common Public Radio Interface (CPRI) IP implements the CPRI Specification V7.0 (2015-10-09). CPRI is a high-speed serial interface for network radio equipment controllers (REC) to receive data from and provide data to remote radio equipment (RE).
The CPRI IP targets high-performance, remote radio network applications. You can configure the CPRI IP as an RE or an REC.
This user guide describes CPRI MAC layer information and does not cover information related to CPRI PHY. For related information:
- For the E-tile CPRI PHY, refer to the About the E-Tile CPRI PHY IP of the E-tile Hard IP User Guide.
- For the F-tile CPRI PHY IP, refer to the F-tile CPRI PHY IP User Guide.
- For the GTS CPRI PHY IP, refer to the GTS CPRI PHY IP User Guide.
Figure 1. Typical CPRI Application on Altera FPGA DevicesExample system implementation with a two-hop daisy chain. Optical links between devices support high performance.