CPRI IP User Guide

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ID 683595
Date 6/13/2025
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Document Table of Contents
Document Table of Contents x
1. About the CPRI IP 2. Getting Started with the CPRI IP 3. CPRI IP Functional Description 4. CPRI IP Signals 5. CPRI IP Registers 6. CPRI Altera® FPGA IP User Guide Archives 7. Document Revision History for the CPRI IP User Guide
1. About the CPRI IP x
1.1. CPRI IP Features 1.2. CPRI IP Device Family and Speed Grade Support 1.3. IP Verification 1.4. Resource Utilization for CPRI IP 1.5. CPRI IP Release Information
1.2. CPRI IP Device Family and Speed Grade Support x
1.2.1. CPRI IP Device Family Support 1.2.2. CPRI IP Device and Transceiver Speed Grade Support
2. Getting Started with the CPRI IP x
2.1. Installation and Licensing 2.2. Generating a CPRI IP 2.3. CPRI IP Parameters 2.4. Integrating the CPRI IP into your Design: Required External Blocks 2.5. Simulating Intel FPGA IP Cores 2.6. Running the CPRI IP Design Example 2.7. CPRI IP Design Example Clocks 2.8. About the Testbench 2.9. Compiling the Full Design and Programming the FPGA
2.1. Installation and Licensing x
2.1.1. Intel FPGA IP Evaluation Mode
2.2. Generating a CPRI IP x
2.2.1. CPRI IP Generated Files
2.4. Integrating the CPRI IP into your Design: Required External Blocks x
2.4.1. Adding the Transceiver TX PLL IP 2.4.2. Adding the Reset Controller 2.4.3. Adding the Transceiver Reconfiguration Controller 2.4.4. Adding the Off-Chip Clean-Up PLL 2.4.5. Adding and Connecting the Single-Trip Delay Calibration Blocks 2.4.6. CPRI IP Transceiver PLL Calibration 2.4.7. Reference and System PLL Clock for your IP Design
2.4.7. Reference and System PLL Clock for your IP Design x
2.4.7.1. System PLL Connections for the Agilex® 7 F-tile Variations 2.4.7.2. System PLL Connections for the Agilex 5 Variations 2.4.7.3. Reset Sequencer Connections for the Agilex 5 Variations
3. CPRI IP Functional Description x
3.1. Interfaces Overview 3.2. CPRI IP Clocking Structure 3.3. CPRI IP Reset Requirements 3.4. Start-Up Sequence Following Reset 3.5. AUX Interface 3.6. Direct IQ Interface 3.7. Ctrl_AxC Interface 3.8. Direct Vendor Specific Access Interface 3.9. Real-Time Vendor Specific Interface 3.10. Direct HDLC Serial Interface 3.11. Direct L1 Control and Status Interface 3.12. L1 Debug Interface 3.13. Media Independent Interface (MII) to External Ethernet Block 3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block 3.15. CPU Interface to CPRI IP Registers 3.16. Auto-Rate Negotiation 3.17. Extended Delay Measurement 3.18. CPRI IP Deterministic Latency 3.19. CPRI IP Transceiver and Transceiver Management Interfaces 3.20. Testing Features
3.2. CPRI IP Clocking Structure x
3.2.1. Example CPRI IP Clock Connections in Different Clocking Modes
3.4. Start-Up Sequence Following Reset x
3.4.1. Start-Up Sequence Interface Signals
3.5. AUX Interface x
3.5.1. AUX Interface Signals 3.5.2. AUX Interface Synchronization 3.5.3. Auxiliary Latency Cycles 3.5.4. Direct Interface CPRI Frame Data Format
3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block x
3.14.1. GMII Normal Mode 3.14.2. Ethernet PCS Bypass Mode 3.14.3. Ethernet PCS Run-Time Switching
3.15. CPU Interface to CPRI IP Registers x
3.15.1. CPU Interface Signals 3.15.2. Accessing the Hyperframe Control Words
3.15.2. Accessing the Hyperframe Control Words x
3.15.2.1. Specifying the Control Word 3.15.2.2. Specifying the Position in the Control Word 3.15.2.3. Retrieving the Hyperframe Control Words 3.15.2.4. Writing the Hyperframe Control Words
3.17. Extended Delay Measurement x
3.17.1. Extended Delay Measurement for Soft Internal Buffers 3.17.2. Extended Delay Measurement for Stratix® 10 Hard FIFOs 3.17.3. Extended Delay Measurement Interface
3.19. CPRI IP Transceiver and Transceiver Management Interfaces x
3.19.1. CPRI Link 3.19.2. Main Transceiver Clock and Reset Signals 3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface 3.19.4. Arria® 10, Stratix® 10, and Agilex® 7 Transceiver Reconfiguration Interface 3.19.5. RS-FEC Interface 3.19.6. Interface to the External Reset Controller 3.19.7. Interface to the External PLL 3.19.8. Transceiver Debug Interface
3.20. Testing Features x
3.20.1. CPRI IP Loopback Modes 3.20.2. CPRI IP Self-Synchronization Feature
4. CPRI IP Signals x
4.1. CPRI IP Core L2 Interface 4.2. CPRI IP Core L1 Direct Access Interfaces 4.3. CPRI IP Core Management Interfaces 4.4. CPRI IP Core Transceiver and Transceiver Management Signals
1. About the CPRI IP
2. Getting Started with the CPRI IP
3. CPRI IP Functional Description
4. CPRI IP Signals
5. CPRI IP Registers
6. CPRI Altera® FPGA IP User Guide Archives
7. Document Revision History for the CPRI IP User Guide

3.20.1. CPRI IP Loopback Modes

Figure 65.  CPRI IP Loopback Modes


Table 53.  Loopback Modes
Tag in Figure Description How to Configure
1 External loopback: Use this configuration to test the full Tx and Rx paths from an application through the CPRI link and back to the application. Connect a CPRI REC host's CPRI Tx interface to its CPRI Rx interface by physically connecting the CPRI IP's high-speed transceiver output pins to its high-speed transceiver input pins.

The connection medium must support the data rate requirements of the CPRI IP.

For a CPRI RE target, you must set tx_enable_force in L1_CONFIG.

2 Transceiver PMA serial forward loopback path is active. Turn on Enable transceiver PMA serial forward loopback path in the parameter editor and set the loop_forward field of the LOOPBACK register to the value 2'b01.
3 Active parallel loopback path does not exercise the transceiver. Turn on Enable parallel forward loopback paths in the parameter editor and set the loop_forward field of the LOOPBACK register to the value 2'b10 (to include the stitching logic to the transceiver) or 2'b11 (to exclude the stitching logic to the transceiver).
4 Reverse loopback path is active. Turn on Enable parallel reversed loopback paths in the parameter editor and set the loop_reversed field of the LOOPBACK register to a non-zero value. The register value specifies the parts of the CPRI frame that participate in the loopback path. Other parts of the CPRI frame are filled in from the local IP.
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