CPRI IP User Guide

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ID 683595
Date 6/13/2025
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Document Table of Contents
Document Table of Contents x
1. About the CPRI IP 2. Getting Started with the CPRI IP 3. CPRI IP Functional Description 4. CPRI IP Signals 5. CPRI IP Registers 6. CPRI Altera® FPGA IP User Guide Archives 7. Document Revision History for the CPRI IP User Guide
1. About the CPRI IP x
1.1. CPRI IP Features 1.2. CPRI IP Device Family and Speed Grade Support 1.3. IP Verification 1.4. Resource Utilization for CPRI IP 1.5. CPRI IP Release Information
1.2. CPRI IP Device Family and Speed Grade Support x
1.2.1. CPRI IP Device Family Support 1.2.2. CPRI IP Device and Transceiver Speed Grade Support
2. Getting Started with the CPRI IP x
2.1. Installation and Licensing 2.2. Generating a CPRI IP 2.3. CPRI IP Parameters 2.4. Integrating the CPRI IP into your Design: Required External Blocks 2.5. Simulating Intel FPGA IP Cores 2.6. Running the CPRI IP Design Example 2.7. CPRI IP Design Example Clocks 2.8. About the Testbench 2.9. Compiling the Full Design and Programming the FPGA
2.1. Installation and Licensing x
2.1.1. Intel FPGA IP Evaluation Mode
2.2. Generating a CPRI IP x
2.2.1. CPRI IP Generated Files
2.4. Integrating the CPRI IP into your Design: Required External Blocks x
2.4.1. Adding the Transceiver TX PLL IP 2.4.2. Adding the Reset Controller 2.4.3. Adding the Transceiver Reconfiguration Controller 2.4.4. Adding the Off-Chip Clean-Up PLL 2.4.5. Adding and Connecting the Single-Trip Delay Calibration Blocks 2.4.6. CPRI IP Transceiver PLL Calibration 2.4.7. Reference and System PLL Clock for your IP Design
2.4.7. Reference and System PLL Clock for your IP Design x
2.4.7.1. System PLL Connections for the Agilex® 7 F-tile Variations 2.4.7.2. System PLL Connections for the Agilex 5 Variations 2.4.7.3. Reset Sequencer Connections for the Agilex 5 Variations
3. CPRI IP Functional Description x
3.1. Interfaces Overview 3.2. CPRI IP Clocking Structure 3.3. CPRI IP Reset Requirements 3.4. Start-Up Sequence Following Reset 3.5. AUX Interface 3.6. Direct IQ Interface 3.7. Ctrl_AxC Interface 3.8. Direct Vendor Specific Access Interface 3.9. Real-Time Vendor Specific Interface 3.10. Direct HDLC Serial Interface 3.11. Direct L1 Control and Status Interface 3.12. L1 Debug Interface 3.13. Media Independent Interface (MII) to External Ethernet Block 3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block 3.15. CPU Interface to CPRI IP Registers 3.16. Auto-Rate Negotiation 3.17. Extended Delay Measurement 3.18. CPRI IP Deterministic Latency 3.19. CPRI IP Transceiver and Transceiver Management Interfaces 3.20. Testing Features
3.2. CPRI IP Clocking Structure x
3.2.1. Example CPRI IP Clock Connections in Different Clocking Modes
3.4. Start-Up Sequence Following Reset x
3.4.1. Start-Up Sequence Interface Signals
3.5. AUX Interface x
3.5.1. AUX Interface Signals 3.5.2. AUX Interface Synchronization 3.5.3. Auxiliary Latency Cycles 3.5.4. Direct Interface CPRI Frame Data Format
3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block x
3.14.1. GMII Normal Mode 3.14.2. Ethernet PCS Bypass Mode 3.14.3. Ethernet PCS Run-Time Switching
3.15. CPU Interface to CPRI IP Registers x
3.15.1. CPU Interface Signals 3.15.2. Accessing the Hyperframe Control Words
3.15.2. Accessing the Hyperframe Control Words x
3.15.2.1. Specifying the Control Word 3.15.2.2. Specifying the Position in the Control Word 3.15.2.3. Retrieving the Hyperframe Control Words 3.15.2.4. Writing the Hyperframe Control Words
3.17. Extended Delay Measurement x
3.17.1. Extended Delay Measurement for Soft Internal Buffers 3.17.2. Extended Delay Measurement for Stratix® 10 Hard FIFOs 3.17.3. Extended Delay Measurement Interface
3.19. CPRI IP Transceiver and Transceiver Management Interfaces x
3.19.1. CPRI Link 3.19.2. Main Transceiver Clock and Reset Signals 3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface 3.19.4. Arria® 10, Stratix® 10, and Agilex® 7 Transceiver Reconfiguration Interface 3.19.5. RS-FEC Interface 3.19.6. Interface to the External Reset Controller 3.19.7. Interface to the External PLL 3.19.8. Transceiver Debug Interface
3.20. Testing Features x
3.20.1. CPRI IP Loopback Modes 3.20.2. CPRI IP Self-Synchronization Feature
4. CPRI IP Signals x
4.1. CPRI IP Core L2 Interface 4.2. CPRI IP Core L1 Direct Access Interfaces 4.3. CPRI IP Core Management Interfaces 4.4. CPRI IP Core Transceiver and Transceiver Management Signals
1. About the CPRI IP
2. Getting Started with the CPRI IP
3. CPRI IP Functional Description
4. CPRI IP Signals
5. CPRI IP Registers
6. CPRI Altera® FPGA IP User Guide Archives
7. Document Revision History for the CPRI IP User Guide

2.4.1. Adding the Transceiver TX PLL IP

The CPRI IP requires that you generate and connect a TX transceiver PLL IP for V-series, Arria® 10, and Stratix® 10 L- and H-tile device variations. The transceiver PLL IP configures the TX PLL in the transceiver on the device, but you must generate the transceiver PLL IP separately from the CPRI IP in the Quartus® Prime software. If you do not generate and connect the transceiver PLL IP, the CPRI IP does not compile.

In the Stratix® 10 E-tile and Agilex® 7 E- tile device variations, the PHY includes a transceiver TX PLL and you do not need to instantiate and connect a TX transceiver PLL IP.

You can use IP Catalog to generate the external PLL IP that configures a TX PLL on the device. In the IP Catalog, select an IP that configures an appropriate PLL on your target device.

For your Stratix V, Arria V, and Cyclone V designs, you can select Intel FPGA PLL (FPLL) or Transceiver PLL in the IP Catalog. In the parameter editor for the TX PLL IP you select, you must set the PLL output frequency to the expected input frequency for the CPRI IP xcvr_ext_pll_clk input signal.

For your Arria® 10 design, you can select Arria 10 Transceiver ATX PLL, Arria 10 Transceiver CMU PLL, or Arria 10 FPLL in the IP Catalog.

For your Stratix® 10 L- and H-tile designs, you can select L-Tile/H-Tile Transceiver ATX PLL Intel Stratix 10 FPGA IP, L-Tile/H-Tile Transceiver CMU PLL Intel Stratix 10 FPGA IP, or L-Tile/H-Tile fPLL Intel Stratix 10 FPGA IP in IP Catalog.

In the parameter editor for the TX PLL IP you select, you must set the following parameter values:

  • Set the PLL output frequency to one half the per-lane data rate of the IP variation, multiplied by the value of the Transmitter local clock division factor parameter of the CPRI IP.

    For example, if your CPRI IP variation has a CPRI line bit rate of 10.1376 Gbps and you set the Transmitter local clock division factor to the value of 1, you must set the TX PLL PLL output frequency parameter to the value of 5068.8 MHz.

  • Set the PLL reference clock frequency to a frequency at which you can drive the TX PLL input reference clock. You must drive the external PLL reference clock input signal at the frequency you specify for this parameter.

    For example, if your CPRI IP variation has a CPRI line bit rate of 10.1376 Gbps and you set the Transmitter local clock division factor parameter to the value of 1, you can set the PLL reference clock frequency to the value of 307.2 MHz.

You must connect the external TX PLL signals and the CPRI IP re transceiver TX PLL interface signals according to the following rules.

Table 13.  Required Connections Between Transceiver TX PLL and CPRI IP Connect the xcvr_ext_pll_clk input signal of the CPRI IP to the pll_clkout, tx_serial_clk, or outclk0 output signal of the external PLL IP. Information about connecting the transceiver TX PLL to the Reset Controller is available in Adding the Reset Controller.
CPRI IP Signal TX PLL Type Device TX PLL Signal
xcvr_ext_pll_clk (input) CMU and ATX PLL Arria® 10 and Stratix® 10 tx_serial_clk
V-series pll_clkout
fPLL Arria® 10 and Stratix® 10 tx_serial_clk
V-series outclk0

If your CPRI IP is an RE target, drive the input signal of the external PLL IP with the output of the off-chip cleanup PLL.

User logic must provide the connections. Refer to the Figure 1 to see how to connect the external TX PLL to a single CPRI IP.

For your Stratix® 10 E-tile and Agilex® 7 E- tile designs, clock signals ehip_clk_806 and ehip_clk_403 handle the clock-crossing in Embedded Multi-die Interconnect Bridge (EMIB) interface. These clocks must be frequency locked to each other. You need to use the E-Tile Transceiver Native PHY IP in PLL mode as the clock source to the CPRI IP as shown in figure below.
Note: The E-Tile Transceiver Native PHY IP used in a PLL mode generates clocks necessary for Application Interface Block (AIB). The PHY includes a transceiver TX PLL that generates PMA high-speed serial clock.
Figure 6. Required External Block for the Stratix® 10 E-tile and Agilex® 7 E- tile Device Variations

You can create E-Tile Transceiver Native PHY from the IP Catalog:
  • Select the E-Tile Transceiver Native PHY
  • In the parameter editor, set the following parameter values:
    • Set the Transceiver configuration rules to PLL
    • Set the SerDes/Output Driver Enable Mode to Disable output drivers
    • Set the PLL output clock frequency to 805.6640625 MHz
    • Set the PLL reference clock frequency to 156.250000 MHz
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