F-Tile CPRI PHY Intel® FPGA IP User Guide

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ID 683284
Date 1/13/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile CPRI PHY Intel® FPGA IP 2. Getting Started 3. IP Parameter Settings 4. Functional Description 5. IP Registers 6. F-Tile CPRI PHY Intel FPGA IP User Guide Archives 7. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide
1. About the F-Tile CPRI PHY Intel® FPGA IP x
1.1. Supported Features 1.2. Block Diagram 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. F-Tile CPRI PHY IP Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. IP Core Testbenches
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. Specifying the IP Core Parameters and Options x
2.2.1. Reference and System PLL Clock for your IP Design
3. IP Parameter Settings x
3.1. Design Example Parameters 3.2. Analog Parameters for F-Tile IPs 3.3. Adaptation Parameters
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency 4.2.2. Calculation for 64b/66b Datapath
1. About the F-Tile CPRI PHY Intel® FPGA IP
2. Getting Started
3. IP Parameter Settings
4. Functional Description
5. IP Registers
6. F-Tile CPRI PHY Intel FPGA IP User Guide Archives
7. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide

1. About the F-Tile CPRI PHY Intel® FPGA IP

Updated for:
Intel® Quartus® Prime Design Suite 24.3
IP Version 5.0.0

The F-Tile CPRI PHY Intel® FPGA IP implements the physical layer (layer 1) specification in the Agilex™ 7 devices based on the Common Public Radio Interface (CPRI) v7.0 Specification (2015-10-09).


Section Content
Supported Features
Block Diagram
Device Family Support
Device Speed Grade Support
Resource Utilization
F-Tile CPRI PHY IP Release Information

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