E-Tile Hard IP for Ethernet Release Notes

ID 683582
Date 4/29/2024
Document Table of Contents

2.3. E-Tile Hard IP for Ethernet Intel® FPGA IP v23.0.0

Table 3.  v23.0.0 2023.01.31
Quartus® Prime Version Description Impact
22.4 Corrected the E-Tile Ethernet IP generation error when adding support for the Agilex™ 7 device in Quartus.
Updated signal properties for platform design. Changed the display signal property from reset to reset_n.
Fixed tri-state buffer/node warning.
Enabled Passing PMA Adaption parameters to native PHY in 100G PTP FEC mode. When enabled, IP parameters are passed to PMA in 100G PTP FEC mode.
Fixed critical warnings for 100G E-Tile Dynamic Reconfiguration Design Example.
When Enable Native PHY Debug Master Endpoint(NPDME) parameter is disabled, access to the Native PHY PMA capability registers is enabled.