E-Tile Hard IP for Ethernet Release Notes

ID 683582
Date 4/29/2024
Document Table of Contents

2.4. E-Tile Hard IP for Ethernet Intel® FPGA IP v22.0.0

Table 4.  v22.0.0 2022.09.26
Quartus® Prime Version Description Impact
22.3 Added support for E-Tile Dynamic Reconfiguration Design Example that toggles o_sl_rx_pcs66_am_valid signal for non-RSFEC modes
Corrected the o_rx_clkout [n] signal width
Corrected port name mismatch in the TX MII Interface section
Added support for E-tile 25G/100GE MAC, PHY Hard IP with run-time dynamic reconfiguration
Added support for E-tile RX PMA custom configuration for 100GE-CR2 (PAM4 with ANLT)
Updated the "Conceptual Overview of General IP Core Reset Logic" table
Renamed the parameter Enable SyncE to Enable SyncE With Dedicated Reference Clock Per Channel
Added a table row for Disable ANLT Golden Recipe
Added support for Agilex™ 7 E-tile 100G Ethernet MAC, PHY IP with dynamic reconfiguration
Provided information about E-Tile Ethernet Hard IP does not support AN & LT with an Optical Cable
Provided information about the ability to select internal or external CPU for the 100G Ethernet Dynamic Reconfiguration.
Changed the IP parameter Enable SyncE in EHIP to Enable SyncE with Dedicated Reference Clock Per Channel
Removed the i_rsfec_tx_rst_n/i_rsfec_rx_rst_n resets ports on the generated E-Tile Hard IP for Ethernet.