2.1. E-Tile Hard IP for Ethernet Intel® FPGA IP v24.1.0
2.2. E-Tile Hard IP for Ethernet Intel® FPGA IP v24.0.0
2.3. E-Tile Hard IP for Ethernet Intel® FPGA IP v23.0.0
2.4. E-Tile Hard IP for Ethernet Intel® FPGA IP v22.0.0
2.5. E-Tile Hard IP for Ethernet Intel® FPGA IP v21.0.0
2.6. E-Tile Hard IP for Ethernet Intel® FPGA IP v20.3.0
2.7. E-Tile Ethernet IP for Intel Agilex FPGA v20.2.1
2.8. E-Tile Hard IP for Ethernet Intel® FPGA IP v20.2.0
2.9. E-Tile Hard IP for Ethernet Intel® FPGA IP v19.4.0
2.10. E-Tile Hard IP for Ethernet Intel® FPGA IP v19.3.0
2.11. E-Tile Hard IP for Ethernet Intel® FPGA IP v19.2
2.12. E-tile Hard IP for Ethernet Intel® FPGA IP v19.1
2.13. E-Tile Hard IP for Ethernet Intel® FPGA IP v18.1.1
2.14. E-Tile Hard IP for Ethernet Intel® FPGA IP v18.1
2.15. E-Tile Hard IP for Ethernet Intel® FPGA IP v18.0
3.1. E-Tile Ethernet IP for Intel Agilex FPGA v24.1.0
3.2. E-Tile Ethernet IP for Intel Agilex FPGA v24.0.1
3.3. E-Tile Ethernet IP for Intel Agilex FPGA v23.0.0
3.4. E-Tile Ethernet IP for Intel Agilex FPGA v22.0.0
3.5. E-Tile Ethernet IP for Intel Agilex FPGA v21.0.0
3.6. E-Tile Ethernet IP for Intel Agilex FPGA v20.2.0
3.7. E-Tile Ethernet IP for Intel Agilex FPGA v20.1.1
3.8. E-Tile Ethernet IP for Intel Agilex FPGA v19.4.0
3.9. E-Tile Ethernet IP for Intel Agilex FPGA v19.3.0
2.4. E-Tile Hard IP for Ethernet Intel® FPGA IP v22.0.0
| Quartus® Prime Version | Description | Impact |
|---|---|---|
| 22.3 | Added support for E-Tile Dynamic Reconfiguration Design Example that toggles o_sl_rx_pcs66_am_valid signal for non-RSFEC modes | — |
| Corrected the o_rx_clkout [n] signal width | ||
| Corrected port name mismatch in the TX MII Interface section | ||
| Added support for E-tile 25G/100GE MAC, PHY Hard IP with run-time dynamic reconfiguration | ||
| Added support for E-tile RX PMA custom configuration for 100GE-CR2 (PAM4 with ANLT) | ||
| Updated the "Conceptual Overview of General IP Core Reset Logic" table | ||
| Renamed the parameter Enable SyncE to Enable SyncE With Dedicated Reference Clock Per Channel | ||
| Added a table row for Disable ANLT Golden Recipe | ||
| Added support for Agilex™ 7 E-tile 100G Ethernet MAC, PHY IP with dynamic reconfiguration | ||
| Provided information about E-Tile Ethernet Hard IP does not support AN & LT with an Optical Cable | ||
| Provided information about the ability to select internal or external CPU for the 100G Ethernet Dynamic Reconfiguration. | ||
| Changed the IP parameter Enable SyncE in EHIP to Enable SyncE with Dedicated Reference Clock Per Channel | ||
| Removed the i_rsfec_tx_rst_n/i_rsfec_rx_rst_n resets ports on the generated E-Tile Hard IP for Ethernet. |