AN 949: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices

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ID 683565
Date 6/23/2021
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Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices x
1.1. Hardware and Software Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204C Intel® FPGA IP and DAC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 949: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Transmitter Data Link Layer Test 1.3.2. Transmitter Transport Layer Test 1.3.3. Deterministic Latency - Subclass 1
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices

1.3.3. Deterministic Latency - Subclass 1

The deterministic latency for the JESD204C Intel® FPGA IP is verified by transmitting known signal pattern from the FPGA to AD9081 through JESD204C interface. The DAC generates analog output, which is fed back to the FPGA through I/O and the appropriate voltage translator circuit. The FPGA detects the DAC output signal and calculates the clock interval between the FPGA sample generation and the DAC output detection, which gives the latency for the JESD204C Intel® FPGA IP. This test is repeated for a minimum of 10 cycles and the latency during each iteration is observed. The observed latency must be in the boundary of 1 or 2 clock cycles.

Figure 6. Deterministic Latency Measurement Block Diagram
Figure 7. Voltage Level Translator Circuit
Table 3.  Deterministic Latency Measurement Test Cases
Test Case Objective Description Passing Criteria
DL.1 Check the FPGA SYSREF single detection. Check that the FPGA detects the first rising edge of SYSREF pulse.
  • Read the status of sysref_singledet (bit[2]) identifier in the sysref_ctrl register at address 0x54.
  • Read the status of sysref_lemc_err (bit[0]) identifier in the tx_err register at address 0x60.

The sysref_alwayson (0x54 bit[1]) should be set to ‘1’ for sysref_lemc_err to function as expected.

  • The value of sysref_singledet identifier should be zero.
  • The value of sysref_lemc_err identifier should be zero.
DL.2 Check the data latency during user data phase. Check that the data latency is consistent for every FPGA and AD9081 reset and power cycle using tx_ana_dl_sig_in.
  • The deterministic latency measurement block in the FPGA has a counter to measure the link clock count.
 The link clock count value should only drift within 1 to 2 link clocks for at least 10 power cycle tests.
Figure 8. Deterministic Latency Measurement Timing Diagram
Level Two Title