AN 949: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices

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ID 683565
Date 6/23/2021
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Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices x
1.1. Hardware and Software Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204C Intel® FPGA IP and DAC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 949: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Transmitter Data Link Layer Test 1.3.2. Transmitter Transport Layer Test 1.3.3. Deterministic Latency - Subclass 1
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Intel® Stratix® 10 E-Tile Devices

1.5. Test Results

The following table contains the possible results and their definition.

Table 5.  Results Definition
Result Definition
PASS The Device Under Test (DUT) was observed to exhibit conformant behavior.
PASS with comments The DUT was observed to exhibit conformant behavior. However, an additional explanation of the situation is included (example: due to time limitations, only a portion of the testing was performed).
FAIL The DUT was observed to exhibit non-conformant behavior.
Warning The DUT was observed to exhibit behavior that is not recommended.
Refer to comments From the observations, a valid pass or fail cannot be determined. An additional explanation of the situation is included.

The following table shows the results for link establishment test and transport layer test for 21 modes of different lane rates of the JESD204C DAC.

Table 6.  Results for Link Establisment Test and Transport Layer Test
No. JESD204C DAC Mode L M F S E N DAC Sampling Clock

(MHz)

 FPGA Device Clock

(MHz)

 Course Interpolation Fine Interpolation Lane Rate

(Gbps)

 Link Status (LL.1, LL.2) Sample PRBS Test (TL.1, TL.2)
1 1 1 4 8 1 1 16 11796.48 245.76 12 4 16.22016 Pass Pass
2 2 1 2 4 1 1 16 11796.48 245.76 12 4 16.22016 Pass Pass
3 3 2 8 8 1 1 16 11796.48 245.76 12 2 16.22016 Pass Pass
4 5 2 4 4 1 1 16 11796.48 245.76 12 2 16.22016 Pass Pass
5 6 2 2 2 1 1 16 11796.48 245.76 12 1 16.22016 Pass Pass
6 7 3 12 8 1 1 16 5898.24 245.76 12 2 16.22016 Pass Pass
7 8 3 6 4 1 1 16 11796.48 245.76 12 2 16.22016 Pass Pass
8 9 4 8 4 1 1 16 11796.48 245.76 12 2 16.22016 Pass Pass
9 10 4 4 2 1 1 16 11796.48 245.76 12 1 16.22016 Pass Pass
10 11 4 16 8 1 1 16 8847.36 184.32 12 4 12.16512 Pass Pass
11 12 4 2 1 1 1 16 2949.12 184.32 2 1 12.16512 Pass Pass
12 14 6 12 4 1 1 16 8847.36 184.32 12 2 12.16512 Pass Pass
13 15 8 8 2 1 1 16 8847.36 184.32 12 1 12.16512 Pass Pass
14 16 8 16 4 1 1 16 5898.24 184.32 8 2 12.16512 Pass Pass
15 17 8 4 1 1 1 16 11796.48 184.32 8 1 12.16512 Pass Pass
16 18 8 2 1 2 1 16 11796.48 184.32 4 1 12.16512 Pass Pass
17 20 8 1 1 4 1 16 5898.24 184.32 1 1 12.16512 Pass Pass
18 21 4 8 8 2 1 16 5898.24 245.76 12 2 8.11008 Pass Pass
19 30 4 4 4 2 1 16 5898.24 184.32 8 1 12.16512 Pass Pass
20 31 4 4 8 4 1 16 5898.24 184.32 8 1 12.16512 Pass Pass
21 33 4 2 8 8 1 16 5898.24 184.32 4 1 12.16512 Pass Pass

The following table shows the deterministic latency test results for different JESD204C modes and lane rates.

Table 7.  Result for Deterministic Latency Test
No. JESD204C JRx Mode Test L M F Data Rate (Gbps) DAC Sampling Clock (MHz) FPGA Link Clock (MHz) FPGA Frame Clock (MHz) Result TPL Phase Offset Latency (Frame Clock Cycles) Latency (Equivalent Link Clock Cycles)
1 1 DL.1 1 4 8 16.22016 11796.48 122.88 245.76 Pass 2 80 40
DL.2 1 4 8 16.22016 11796.48 122.88 245.76 Pass
2 2 DL.1 1 2 4 16.22016 11796.48 122.88 245.76 Pass 2 62 31
DL.2 1 2 4 16.22016 11796.48 122.88 245.76 Pass
3 3 DL.1 2 8 8 16.22016 11796.48 122.88 245.76 Pass 2 80 40
DL.2 2 8 8 16.22016 11796.48 122.88 245.76 Pass
4 5 DL.1 2 4 4 16.22016 11796.48 122.88 245.76 Pass 2 63 31
DL.2 2 4 4 16.22016 11796.48 122.88 245.76 Pass
5 6 DL.1 2 2 2 16.22016 11796.48 122.88 245.76 Pass 2 57 28
DL.2 2 2 2 16.22016 11796.48 122.88 245.76 Pass
6 7 DL.1 3 12 8 16.22016 5898.24 122.88 245.76 Pass 2 99 49
DL.2 3 12 8 16.22016 5898.24 122.88 245.76 Pass
7 8 DL.1 3 6 4 16.22016 11796.48 122.88 245.76 Pass 2 63 31
DL.2 3 6 4 16.22016 11796.48 122.88 245.76 Pass
8 9 DL.1 4 8 4 16.22016 11796.48 122.88 245.76 Pass 2 63 31
DL.2 4 8 4 16.22016 11796.48 122.88 245.76 Pass
9 10 DL.1 4 4 2 16.22016 11796.48 122.88 245.76 Pass 2 57 28
DL.2 4 4 2 16.22016 11796.48 122.88 245.76 Pass
10 11 DL.1 4 16 8 12.16512 8847.36 92.16 184.32 Pass 2 80 40
DL.2 4 16 8 12.16512 8847.36 92.16 184.32 Pass
11 12 DL.1 4 2 1 12.16512 2949.12 92.16 184.32 Pass 2 50 25
DL.2 4 2 1 12.16512 2949.12 92.16 184.32 Pass
12 14 DL.1 6 12 4 12.16512 8847.36 92.16 184.32 Pass 2 62 31
DL.2 6 12 4 12.16512 8847.36 92.16 184.32 Pass
13 15 DL.1 8 8 2 12.16512 8847.36 92.16 184.32 Pass 2 56 28
DL.2 8 8 2 12.16512 8847.36 92.16 184.32 Pass
14 16 DL.1 8 16 4 12.16512 5898.24 92.16 184.32 Pass 2 64 32
DL.2 8 16 4 12.16512 5898.24 92.16 184.32 Pass
15 17 DL.1 8 4 1 12.16512 11796.48 92.16 184.32 Pass 2 41 20
DL.2 8 4 1 12.16512 11796.48 92.16 184.32 Pass
16 18 DL.1 8 2 1 12.16512 11796.48 92.16 184.32 Pass 2 37 18
DL.2 8 2 1 12.16512 11796.48 92.16 184.32 Pass
17 20 DL.1 8 1 1 12.16512 5898.24 92.16 184.32 Pass 2 34 17
DL.2 8 1 1 12.16512 5898.24 92.16 184.32 Pass
18 21 DL.1 8 8 8 8.11008 5898.24 61.44 245.76 Pass 1F 61 15
DL.2 8 8 8 8.11008 5898.24 61.44 245.76 Pass
19 30 DL.1 4 4 4 12.16512 5898.24 92.16 184.32 Pass 2 56 28
DL.2 4 4 4 12.16512 5898.24 92.16 184.32 Pass
20 31 DL.1 4 4 8 12.16512 5898.24 92.16 184.32 Pass 2 58 29
DL.2 4 4 8 12.16512 5898.24 92.16 184.32 Pass
21 33 DL.1 4 2 8 12.16512 5898.24 92.16 184.32 Pass 2 45 24
DL.2 4 2 8 12.16512 5898.24 92.16 184.32 Pass
Level Two Title