R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683544
Date 12/19/2022

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Document Table of Contents

2.4. Root Port BFM

The basic Root Port BFM provides a Verilog HDL task‑based interface to request transactions to issue on the PCI Express link. The Root Port BFM also handles requests received from the PCI Express link. The following figure shows the major modules in the Root Port BFM.

Figure 23. Root Port BFM

These modules implement the following functionality:

  • BFM Log Interface, altpcietb_g3bfm_log.v and altpcietb_bfm_rp_gen5_x16.sv: The BFM Log Interface provides routines for writing commonly formatted messages to the simulator standard output and optionally to a log file. It also provides controls that stop simulations on errors.
  • BFM Read/Write Request Functions, altpcietb_bfm_rp_gen5_x16.sv: These functions provide the basic BFM calls for PCI Express read and write requests.
  • BFM Configuration Functions, altpcietb_g3bfm_configure.v : These functions provide the BFM calls to request a configuration of the PCI Express link and the Endpoint Configuration Space registers.
  • BFM shared memory, altpcietb_g3bfm_shmem.v: This module provides the Root Port BFM shared memory. It implements the following functionality:
    • Provides data for TX write operations
    • Provides data for RX read operations
    • Receives data for RX write operations
    • Receives data for received completions
  • BFM Request Interface, altpcietb_g3bfm_req_intf.v: This interface provides the low-level interface between the altpcietb_g3bfm_rdwr and altpcietb_g3bfm_configure procedures or functions and the Root Port RTL Model. This interface stores a write-protected data structure containing the sizes and values programmed in the BAR registers of the Endpoint. It also stores other critical data used for internal BFM management.
  • altpcietb_g3bfm_rdwr.v: This module contains the low-level read and write tasks.
  • Avalon‑ST Interfaces, altpcietb_g3bfm_vc_intf_ast_common.v: These interface modules handle the Root Port interface model. They take requests from the BFM request interface and generate the required PCI Express transactions. They handle completions received from the PCI Express link and notify the BFM request interface when requests are complete. Additionally, they handle any requests received from the PCI Express link, and store or fetch data from the shared memory before generating the required completions.

In the PIO design example, the apps_type_hwtcl parameter is set to 3. The tests run under this parameter value are defined in ebfm_cfg_rp_ep_rootport, find_mem_bar and downstream_loop.

The function ebfm_cfg_rp_ep_rootport is described in altpcietb_g3bfm_configure.v. This function performs the steps necessary to configure the root port and the endpoint on the link. It includes:
  • Root port memory allocation
  • Root port configuration space (base limit, bus number, etc.)
  • Endpoint configuration (BAR, Bus Master enable, maxpayload size, etc.)

The functions find_mem_bar and downstream_loop in altpcietb_bfm_rp_gen5_x16.sv return the BAR implemented and perform the memory Write and Read accesses to the BAR, respectively.