R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
A newer version of this document is available. Customers should click here to go to the newest version.
Visible to Intel only — GUID: jiy1622589806130
Ixiasoft
Visible to Intel only — GUID: jiy1622589806130
Ixiasoft
1.1.1. Credit Value Initialization and Return
The following table shows an example of a posted 1024-bit write sequence consuming one posted header credit and eight posted data credits.
Header | H0 | |||||||
Data | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
A non-posted read sequence consumes one non-posted header credit only as shown in the table below.
Header | H0 |
Data |