R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683544
Date 12/13/2021

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2.5. Compiling the Design Example

  1. Navigate to <project_dir>/intel_rtile_pcie_ast_0_example_design/ and open pcie_ed.qpf.
  2. If you select a specific development kit when generating the design example, the VID-related settings are included in the .qsf file and you are not required to add them manually. Note that these settings are board-specific.
  3. On the Processing menu, select Start Compilation.

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