R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683544
Date 10/04/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2. Quick Start Guide

Using the Intel® Quartus® Prime Pro Edition software, you can generate a programmed I/O (PIO) design example for the Intel® FPGA R-tile Avalon® -ST Hard IP for PCI Express* IP core. The generated design example reflects the parameters that you specify. The PIO example transfers data from a host processor to a target device. It is appropriate for low-bandwidth applications. This design example automatically creates the files necessary to simulate and compile in the Intel® Quartus® Prime Pro Edition software. You can download a compiled version of this PIO design example to the Intel® Agilex™ I-Series ES0 FPGA Development Board for evaluation. To download to custom hardware, update the Intel® Quartus® Prime Settings File (.qsf) with the correct pin assignments . However, note that hardware testing is not fully supported because the Debug Toolkit is not available in the 21.3 Intel® Quartus® Prime release.

Figure 8. Development Steps for the Design Example