R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683544
Date 10/04/2021

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Document Table of Contents

2.2. Generating the Design Example

Figure 10. Procedure
  1. In the Intel® Quartus® Prime Pro Edition software, create a new project (File > New Project Wizard).
  2. Specify the Directory, Name, and Top-Level Entity.
  3. For Project Type, accept the default value, Empty project. Click Next.
  4. For Add Files click Next.
  5. For Family, Device & Board Settings under Family, select Intel® Agilex™ I-Series.
  6. Select the Target Device for your design.
  7. Click Finish.
  8. In the IP Catalog locate and add the Intel R-Tile Avalon® -ST Hard IP for PCI Express* .
  9. In the New IP Variant dialog box, specify a name for your IP. Click Create.
  10. On the Top-Level Settings and PCIe* Settings tabs, specify the parameters for your IP variation.
  11. On the Example Designs tab, make the following selections:
    1. For Available Example Designs, currently only PIO is available.
    2. For Example Design Files, turn on the Simulation and Synthesis options. If you do not need these simulation or synthesis files, leaving the corresponding option(s) turned off significantly reduces the example design generation time.
    3. For Generated HDL Format, only Verilog is available in the current release.
    4. For Target Development Kit, select the appropriate development kit.
      Note: If you select None, the generated design example targets the device you specified in Step 5 above. If you intend to test the design in hardware, make the appropriate pin assignments in the .qsf file. You can also use the pin planner tool to make pin assignments.
      Note: If you select a development kit, the device on that board overwrites the device selected in the Intel® Quartus® Prime project if the devices are different.
  12. Select Generate Example Design to create a design example that you can simulate. When the prompt asks you to specify the directory for your example design, you can accept the default directory, ./intel_rtile_pcie_ast_0_example_design, or choose another directory.
    Figure 11. IP Parameter Editor Screen for Generating Example Design
  13. Click Finish. You may save your .ip file when prompted, but it is not required to be able to use the example design.
  14. Open the example design project.
  15. Compile the example design project to generate the .sof file for the complete example design.
  16. Close your example design project.
    Note that you cannot change the PCIe pin allocations in the Intel® Quartus® Prime project. However, to ease PCB routing, you can take advantage of the lane reversal and polarity inversion features supported by this IP.