L-Tile and H-Tile Avalon® Memory-mapped+ Intel® FPGA IP for PCI Express* User Guide
ID
683527
Date
9/13/2024
Public
1. Introduction
2. Quick Start Guide
3. Block and Interface Descriptions
4. Parameters
5. Designing with the IP Core
6. Registers
7. Design Example and Testbench
8. Document Revision History for Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide
A. Avalon-MM IP Variants Comparison
B. Root Port BFM
C. BFM Procedures and Functions
D. Troubleshooting and Observing the Link Status
E. Root Port Enumeration
2.1. Design Components
2.2. Directory Structure
2.3. Generating the Design Example
2.4. Simulating the Design Example
2.5. Compiling the Design Example and Programming the Device
2.6. Installing the Linux Kernel Driver
2.7. Running the Design Example Application
2.8. Ensuring the Design Example Meets Timing Requirements
6.1.1. Register Access Definitions
6.1.2. PCI Configuration Header Registers
6.1.3. PCI Express Capability Structures
6.1.4. Intel Defined VSEC Capability Header
6.1.5. Uncorrectable Internal Error Status Register
6.1.6. Uncorrectable Internal Error Mask Register
6.1.7. Correctable Internal Error Status Register
6.1.8. Correctable Internal Error Mask Register
C.1. ebfm_barwr Procedure
C.2. ebfm_barwr_imm Procedure
C.3. ebfm_barrd_wait Procedure
C.4. ebfm_barrd_nowt Procedure
C.5. ebfm_cfgwr_imm_wait Procedure
C.6. ebfm_cfgwr_imm_nowt Procedure
C.7. ebfm_cfgrd_wait Procedure
C.8. ebfm_cfgrd_nowt Procedure
C.9. BFM Configuration Procedures
C.10. BFM Shared Memory Access Procedures
C.11. BFM Log and Message Procedures
C.12. Verilog HDL Formatting Functions
3.2.1.4. Bursting Avalon-MM Master (BAM) Interface
The Bursting Avalon® -MM Master module has one user-visible Avalon® -MM Master interface.
The bam_bar_o bus contains the BAR address for a particular TLP. This bus is as an extension of the standard address bus.
Signal Name | Direction | Description |
---|---|---|
bam_pfnum_o[PFNUM_WIDTH-1:0] | Output | Avalon® conduit showing function number. |
bam_bar_o[2:0] | Output | 000 : Memory BAR 0 001 : Memory BAR 1 010 : Memory BAR 2 011 : Memory BAR 3 100 : Memory BAR 4 101 : Memory BAR 5 110 : Reserved 111 : Expansion ROM BAR |
bam_waitrequest_i | Input | Avalon® -MM wait request signal with waitrequestAllowance of 8. |
bam_address_o[BAM_ADDR_WIDTH-1:0] | Output | The width of the Bursting Master's address bus is the maximum of the widths of all the enabled BARs. For BARs narrower than the widest BAR, the address bus' additional most-significant bits are driven to 0. |
bam_byteenable_o[63:0] | Output | The BAM interface supports all contiguous byteenable patterns. |
bam_read_o | Output | |
bam_readdata_i[511:0] | Input | |
bam_readdatavalid_i | Input | |
bam_response_i[1:0] | Input | Reserved. Drive these inputs to 0. |
bam_write_o | Output | |
bam_writedata_o[511:0] | Output | |
bam_burstcount_o[3:0] | Output |
For more details on these interface signals, refer to the Avalon® Interface Specifications.
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