Multi Channel DMA IP for PCI Express* Design Example User Guide
ID
683517
Date
8/04/2025
Public
3.5.1. Hardware Requirements
3.5.2. Software Requirements
3.5.3. Set Up the Hardware and Program the FPGA
3.5.4. Configuration Changes from BIOS
3.5.5. Installing the Required Kernel Version for Ubuntu v24.04
3.5.6. Set the Boot Parameters
3.5.7. MCDMA Custom Driver
3.5.8. MCDMA DPDK Poll Mode Driver
3.5.9. MCDMA Kernel Mode Network Device Driver
2.1.3. F-Tile MCDMA IP - Design Examples for Endpoint
Design Example | MCDMA Settings | Driver Support | App Support | |
---|---|---|---|---|
User Mode | Interface Type | |||
AVMM DMA | Multi-Channel DMA |
AVMM | Custom |
Perfq app |
DPDK |
Mcdma_test | |||
BAM + MCDMA |
Custom | Perfq app | ||
DPDK | Mcdma_test | |||
BAM + BAS + MCDMA |
Custom | Perfq app | ||
DPDK | Mcdma_test | |||
Device-side Packet Loopback | Multi-Channel DMA |
AVST 1 Port | Custom |
Perfq app |
DPDK |
Mcdma_test | |||
Netdev |
Netdev_app | |||
BAM + MCDMA |
Custom | Perfq app | ||
DPDK | Mcdma_test | |||
Netdev | Netdev_app | |||
BAM + BAS + MCDMA |
Custom |
Perfq app | ||
DPDK |
Mcdma_test | |||
Netdev |
Netdev_app | |||
Packet Generate/Check | Multi-Channel DMA |
Custom |
Perfq app | |
DPDK |
Mcdma_test | |||
BAM + MCDMA |
Custom | Perfq app | ||
DPDK | Mcdma_test | |||
BAM + BAS + MCDMA |
Custom |
Perfq app | ||
DPDK |
Mcdma_test | |||
PIO using MQDMA Bypass Mode | Multi-Channel DMA |
AVMM AVST 1 Port |
Custom |
Perfq app |
DPDK |
Mcdma_test | |||
BAM + MCDMA BAM + BAS + MCDMA |
Custom | Perfq app | ||
DPDK | Mcdma_test | |||
Bursting Master BAM + BAS |
n/a | Custom |
Perfq app | |
DPDK |
Mcdma_test | |||
Data Mover Only | AVMM | Custom |
Perfq app | |
DPDK |
Mcdma_test | |||
Traffic Generator/Checker | BAM + BAS | n/a | Custom |
Perfq app |
DPDK |
Mcdma_test | |||
External Descriptor Controller | Data Mover Only | AVMM | Custom | Perfq app |
Note: F-Tile MCDMA IP design example doesn’t support multiple physical functions and SR-IOV for simulation.
Note: For 2x8 Hard IP modes, simulation is supported on PCIe0 only.
Note: F-Tile MCDMA IP 1x4 design example does not support simulation.
Note: F-Tile does not support simulation with the ModelSim* - Intel® FPGA Edition, Questa* Intel® FPGA Edition, and Xcelium* simulators.
Note: For F-Tile System PLL reference clock requirement, refer to the Multi Channel DMA IP for PCI Express User Guide.
Note: The F-Tile design example supports PIPE mode simulation, which is now the default mode of simulation..
For information about supported simulators, refer to Supported Simulators.
Refer to Table MCDMA IP Modes and FPGA Development Kit for Design Examples for the supported Hard IP Modes that have Design Example support.