Multi Channel DMA IP for PCI Express* Design Example User Guide

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ID 683517
Date 8/04/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Design Example Detailed Description 3. Design Example Quick Start Guide 4. Multi Channel DMA FPGA IP for PCI Express Design Example User Guide Archives 5. Revision History for the Multi Channel DMA FPGA IP for PCI Express Design Example User Guide
1. Introduction x
1.1. Terms and Acronyms 1.2. MCDMA IP Modes
2. Design Example Detailed Description x
2.1. Design Example Overview 2.2. PIO using MCDMA Bypass Mode 2.3. Avalon-ST Packet Generate/Check 2.4. Avalon-ST Device-side Packet Loopback 2.5. Avalon-MM DMA 2.6. BAM_BAS Traffic Generator and Checker 2.7. External Descriptor Controller
2.1. Design Example Overview x
2.1.1. H-Tile MCDMA IP - Design Examples for Endpoint 2.1.2. P-Tile MCDMA IP - Design Examples for Endpoint 2.1.3. F-Tile MCDMA IP - Design Examples for Endpoint 2.1.4. R-Tile MCDMA IP - Design Examples for Endpoint 2.1.5. Design Example BAR Mappings 2.1.6. Design Example Driver Support
2.2. PIO using MCDMA Bypass Mode x
2.2.1. Avalon-ST PIO using MCDMA Bypass Mode 2.2.2. Avalon-MM PIO using MCDMA Bypass Mode
2.2.1. Avalon-ST PIO using MCDMA Bypass Mode x
2.2.1.1. Single-Port Avalon-ST PIO using MCDMA Bypass Mode
2.2.2. Avalon-MM PIO using MCDMA Bypass Mode x
2.2.2.1. Simulation Results 2.2.2.2. Hardware Test Results
2.3. Avalon-ST Packet Generate/Check x
2.3.1. Single-Port Avalon-ST Packet Generate/Check
2.3.1. Single-Port Avalon-ST Packet Generate/Check x
2.3.1.1. Simulation Waveforms 2.3.1.2. Simulation Log 2.3.1.3. Hardware Test Result
2.4. Avalon-ST Device-side Packet Loopback x
2.4.1. Simulation Results 2.4.2. Hardware Test Results
2.5. Avalon-MM DMA x
2.5.1. Simulation Results 2.5.2. Hardware Test Results
2.6. BAM_BAS Traffic Generator and Checker x
2.6.1. BAM_BAS Traffic Generator and Checker Example Design Register Map
2.7. External Descriptor Controller x
2.7.1. Registers 2.7.2. Hardware Test Results
2.7.1. Registers x
2.7.1.1. GCSR Registers (Base address 64’h00000) 2.7.1.2. QCSR Registers(Base address 64’h10000)
3. Design Example Quick Start Guide x
3.1. Design Example Directory Structure 3.2. Generating the Example Design using Quartus® Prime 3.3. Simulating the Design Example 3.4. Compiling the Example Design in Quartus® Prime 3.5. Running the Design Example Application on a Hardware Setup
3.2. Generating the Example Design using Quartus® Prime x
3.2.1. Procedure
3.3. Simulating the Design Example x
3.3.1. Testbench Overview 3.3.2. Supported Simulators 3.3.3. Example Testbench Flow for DMA Test with Avalon-ST Packet Generate/Check Design Example 3.3.4. Run the Simulation Script 3.3.5. Steps to Run the Simulation 3.3.6. View the Results
3.3.5. Steps to Run the Simulation x
3.3.5.1. Steps to Run the Simulation : QuestaSim* / Questa* Intel® FPGA Edition 3.3.5.2. Steps to Run the Simulation : VCS* / VCS* MX 3.3.5.3. Steps to Run the Simulation : Xcelium*
3.5. Running the Design Example Application on a Hardware Setup x
3.5.1. Hardware Requirements 3.5.2. Software Requirements 3.5.3. Set Up the Hardware and Program the FPGA 3.5.4. Configuration Changes from BIOS 3.5.5. Installing the Required Kernel Version for Ubuntu v24.04 3.5.6. Set the Boot Parameters 3.5.7. MCDMA Custom Driver 3.5.8. MCDMA DPDK Poll Mode Driver 3.5.9. MCDMA Kernel Mode Network Device Driver
3.5.7. MCDMA Custom Driver x
3.5.7.1. Prerequisites 3.5.7.2. PIO Test 3.5.7.3. DMA Test 3.5.7.4. BAM Test 3.5.7.5. BAS Test
3.5.7.1. Prerequisites x
3.5.7.1.1. Install the Linux Kernel Driver 3.5.7.1.2. Enable Virtual Function 3.5.7.1.3. Build and Install the User Space Library 3.5.7.1.4. Build the Reference Application
3.5.7.2. PIO Test x
3.5.7.2.1. Custom PIO Read Write Test
3.5.7.3. DMA Test x
3.5.7.3.1. Avalon-MM DMA (AVMM DMA) 3.5.7.3.2. Avalon-ST Device-side Packet Loopback (Device-side Packet Loopback) 3.5.7.3.3. Avalon-ST Packet Generate/Check (Packet Generate/Check) 3.5.7.3.4. External Descriptor Controller
3.5.7.3.2. Avalon-ST Device-side Packet Loopback (Device-side Packet Loopback) x
3.5.7.3.2.1. DMA Test Beyond 256 Channels
3.5.7.3.3. Avalon-ST Packet Generate/Check (Packet Generate/Check) x
3.5.7.3.3.1. DMA Test Beyond 256 Channels
3.5.8. MCDMA DPDK Poll Mode Driver x
3.5.8.1. Prerequisites 3.5.8.2. PIO Test 3.5.8.3. DMA Test 3.5.8.4. BAM Test 3.5.8.5. BAS Test
3.5.8.1. Prerequisites x
3.5.8.1.1. Install the PMD Driver 3.5.8.1.2. Bind the Device 3.5.8.1.3. Enable Virtual Function
3.5.8.3. DMA Test x
3.5.8.3.1. Avalon-MM DMA (AVMM DMA) 3.5.8.3.2. Avalon-ST Packet Generate/Check (Packet Generate/Check) 3.5.8.3.3. Avalon-ST Device-side Packet Loopback (Device-side Packet Loopback)
3.5.8.3.2. Avalon-ST Packet Generate/Check (Packet Generate/Check) x
3.5.8.3.2.1. DMA Test Beyond 256 Channels
3.5.8.3.3. Avalon-ST Device-side Packet Loopback (Device-side Packet Loopback) x
3.5.8.3.3.1. DMA Test Beyond 256 Channels
3.5.9. MCDMA Kernel Mode Network Device Driver x
3.5.9.1. Prerequisites 3.5.9.2. PIO Test 3.5.9.3. Ping Test
3.5.9.1. Prerequisites x
3.5.9.1.1. Build and Install Netdev Driver 3.5.9.1.2. Enable Virtual Function
1. Introduction
2. Design Example Detailed Description
3. Design Example Quick Start Guide
4. Multi Channel DMA FPGA IP for PCI Express Design Example User Guide Archives
5. Revision History for the Multi Channel DMA FPGA IP for PCI Express Design Example User Guide

2.2.2. Avalon-MM PIO using MCDMA Bypass Mode

Figure 2. MCDMA IP - Avalon-MM Interface PIO Example Design using MCDMA Bypass Mode

This design example enables Avalon-MM PIO master which bypasses the DMA path. The Avalon-MM PIO master allows application to perform single, non-bursting register read/write operation with on-chip memory.

This design example only supports PIO functionality and does not perform DMA operations (similar to the design examples in Avalon-ST PIO using MCDMA Bypass Mode). Hence, the Avalon-MM DMA ports are not connected.

The design example includes the Multi Channel DMA for PCI Express IP Core with the parameters you specified and other supporting components:
  • resetIP – Reset Release IP that holds the Multi Channel DMA in reset until the entire FPGA fabric enters user mode.
  • MEM_PIO – On-chip memory for the PIO operation. Connected to the MCDMA Avalon-MM PIO Master (rx_pio_master) port that is mapped to PCIe BAR2.
Transfer mode option supported in test application software (perfq_app) command line:
  • PIO test: -o

For a description of which driver(s) to use with this design example, refer to Design Example Driver Support.

Note: Metadata Support is not available in AVST Interface mode, PIO using MCDMA Bypass Mode example design.
Note: User-FLR Interface is not available in AVMM Interface mode, PIO Using MCDMA Bypass Mode example design.

Section Content
Simulation Results
Hardware Test Results

Level Two Title