Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP User Guide

ID 683510
Date 4/04/2022

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The SDM Avalon® ST Client IP sends responses to your application using the response interface.
Table 4.  Response Interface
Signal 5 Direction Description
response_ready Input Application logic can assert the response_ready signal whenever it is able to receive a response.
response_valid Output The SDM asserts response_valid to indicate that response_data is valid.
response_data[31:0] Output The SDM drives response_data to provide the requested information. The first word of the response is a header that identifies the command that the SDM is providing. Refer to Command List and Description for definitions of the commands.
response_startofpacket Output The response_startofpacket asserts in the first cycle of a response packet.
response_endofpacket Output The response_endofpacket asserts in the last cycle of a response packet.
Figure 5. Timing for Avalon® ST Response Packet

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