Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP User Guide

Download PDF
ID 683510
Date 4/04/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Mailbox Client with Avalon® Streaming Interface Intel FPGA IP Overview
1. Mailbox Client with Avalon® Streaming Interface Intel FPGA IP Overview x
1.1. Device Family Support 1.2. Commands and Responses 1.3. Mailbox Client with Avalon® Streaming Interface Intel FPGA IP User Guide Document Archives 1.4. Document Revision History for the Mailbox Client with Avalon® Streaming Interface Intel FPGA IP User Guide
1.1. Device Family Support x
1.1.1. Parameters 1.1.2. Interfaces
1.1.2. Interfaces x
1.1.2.1. Clock and Reset Interfaces 1.1.2.2. Command Interface 1.1.2.3. Response Interface 1.1.2.4. Command Status Interface
1.2. Commands and Responses x
1.2.1. Operation Commands 1.2.2. Error Code Responses 1.2.3. Error Code Recovery
1. Mailbox Client with Avalon® Streaming Interface Intel FPGA IP Overview

1.1.2.1. Clock and Reset Interfaces

Table 2.  Clock and Reset Interfaces
Signal Name Direction Description
in_clk Input This is the clock for the Avalon® streaming interfaces. The maximum frequency in 250 MHz.
in_reset Input This is an active high reset. Assert in_reset to reset the Mailbox Client with Avalon® streaming interface Intel® FPGA IP (Mailbox Client with Avalon® ST IP). When the in_reset signal asserts, the SDM must flush any pending activity from the Mailbox Client with Avalon® ST IP. The SDM continues to process commands from other clients.
To ensure the Mailbox Client with Avalon® ST IP functions correctly when the device enters user mode, your design must include the Reset Release Intel® FPGA IP to hold the reset until the FPGA fabric entered user mode. Intel recommends using a reset synchronizer when connecting the user reset or output of the Reset Release IP to the reset port of the Mailbox Client with Avalon® ST IP. To implement the reset synchronizer, use the Reset Bridge Intel® FPGA IP available in the Platform Designer.
Note: For IP instantiation and connection guidelines in the Platform Designer, refer to the Required Communication and Host Components for the Remote System Update Design Example figure in the Intel® Agilex™ Configuration User Guide.
Level Two Title