R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 7/08/2024
Document Table of Contents

4.1.2. Resets

Table 47.  Resets
Name Direction Description EP/RP/BP/PIPE-D Asynchronous / Synchronous
pin_perst_n Input

This is the reset signal from the board. This pin is not available to the FPGA user logic. If you want to use the PERST# signal in user logic or in the Intel Signal Tap tool, you need to use the pin_perst_n_o signal.

EP/RP/BP/PIPE-D Asynchronous
pin_perst0_n, pin_perst1_n Input These are the reset signals from the board. These inputs ports are only available when using the Configuration Mode 1(2x8) and the parameter Enable Independent Perst Pins is set to Enable.
Note: You must have a weak pull-down on the pin_perst0_n/pin_perst1_n pins if the corresponding port is not supplied with a reference clock (refclk0/1) during the FPGA configuration. Failing to meet this requirement may cause both ports to fail to link up when pin_perst_n is toggled once configuration is complete and the reference clock (refclk0/1) is not available. Toggling pin_perst_n or the corresponding pin_perst0_n/pin_perst1_n after the FPGA configuration completion will not recover the links and the FPGA will need to be reconfigured.
EP Asynchronous
pin_perst_n_o Output This output signal to the FPGA fabric indicates if PERST# is asserted. EP/RP/BP/PIPE-D Asynchronous
ninit_done Input

A "1" on this active-low signal indicates that the FPGA device is not yet fully configured. A "0" indicates the device has been configured and is in normal operating mode.

You need to instantiate the Reset Release IP and connect the output of that IP to ninit_done.

EP/RP/BP/PIPE-D Asynchronous
pX_reset_status_n_o Output

This active-low signal is held low until pin_perst_n has been deasserted and the PCIe Hard IP has come out of reset. This signal is synchronous to coreclkout_hip.

When port bifurcation is used, there is one such signal for each Avalon® Streaming interface. Signals for different interfaces are differentiated by the prefixes p<n>.

Traffic between the user logic in the FPGA core and the IP can start when pX_reset_status_n_o is asserted high.

EP/RP/BP Synchronous to coreclkout_hip.
pX_slow_reset_status_n_o Output This is the equivalent signal for pX_reset_status_n_o in the slow_clk domain. EP/RP/BP Synchronous to slow_clk.
pX_cold_perst_n_i Input

When enabled, these active-low signals independently trigger cold resets to individual PCIe Controllers.

If these inputs are not used, they should be tied off to 1.

EP/RP/BP Synchronous to coreclkout_hip.
pX_warm_perst_n_i Input

When enabled, these active-low signals independently trigger warm resets to individual PCIe Controllers.

If these inputs are not used, they should be tied off to 1.

EP/RP/BP Synchronous to coreclkout_hip.
pX_ip_rst_n_o Output These active-low output signals are exposed to the Application logic and indicate the status of the Hard Reset Controller triggering resets to individual PCIe Controllers. EP/RP/BP Synchronous to coreclkout_hip.
LnX_pipe_direct_reset_status_n (X = 0 - 15) Output This active-low per-lane signal is held low until the PHY RX path is out of reset, and when deasserted is an indication to the application logic that the RX data transfer is beginning. PIPE-D Synchronous to pipe_direct_pld_tx_clk_out_o.
LnX_pipe_direct_pld_pcs_rst_n_i (X = 0 - 15) Input This is the per-lane PHY channel reset signal. The Soft IP Controller must release this signal after the per-lane LnX_pipe_direct_tx_transfer_en_o signal is asserted. Follow the reset sequence as shown in PIPE Direct Reset Sequence. PIPE-D Asynchronous