Generic Flash Programmer User Guide: Intel® Quartus® Prime Standard Edition

ID 683491
Date 5/15/2019
Document Table of Contents

1.2. Quad SPI Flash Byte-Addressing

Quad SPI flash devices typically support either 3-byte addressing, 4-byte addressing, or both for programming operations. You can only configure Intel® FPGAs with a flash memory device with byte addressing that is compatible with the Intel® FPGA that you plan to configure.

The following table specifies the byte-addressing compatibility of Intel® FPGAs for supported flash memory devices:

Table 2.   Intel® FPGA Required Flash Memory Byte Addressing
FPGA Devices Required Flash Memory Byte Addressing
Intel® Arria® 10 devices 4-byte addressing
Intel® Cyclone® 10 LP devices 3-byte addressing
Arria® V, Cyclone® V, Stratix® V series devices
  • 3-byte addressing (limited memory address access1)
  • 4-byte addressing
Cyclone® IV, Cyclone® II, Cyclone® III, Arria® GX, Arria® II, Stratix® II, Stratix® III, Stratix® IV, Stratix® IV devices 3-byte addressing

Adding Dummy Clock Cycles

Flash memory devices must read either a 24-bit (3-byte) address, or 32-bit (4-byte) address before the flash device can start receiving data to write to the flash memory, or before outputting the data after the flash memory device receives a read command. Therefore, you must specify (or select a flash memory template that specifies) an appropriate dummy clock cycle value for the flash memory device, as Defining a New Flash Memory Configuration Device describes.

Figure 2.  Reading Configuration Data from Flash (3-Byte and 4-Byte Addressing)
1 Flash devices that exceed 128 megabits (Mb) density require 4-byte addressing to access the memory space higher than 128 Mb. For flash devices that do not support non-volatile, 4-byte addressing setting, the FPGA cannot read the configuration image that has a start address beyond 128Mb. For the remote system update application, the FPGA cannot store images beyond 128Mb.

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