Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide
ID
683486
Date
7/12/2024
Public
1. About the Low Latency E-Tile 40G Ethernet Intel® FPGA IP
2. Low Latency E-Tile 40G Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide Archives
11. Comparison Between Low Latency E-Tile 40G Ethernet Core and Low Latency 40GbE IP Core
12. Document Revision History for Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Specifying the Low Latency E-Tile 40G Ethernet IP Core Parameters and Options
3.3. Simulating the IP Core
3.4. Generated File Structure
3.5. Integrating Your IP Core in Your Design
3.6. Low Latency E-Tile 40G Ethernet IP Core Testbench
3.7. Compiling the Full Design and Programming the FPGA
6.9. Flow Control Interface
Flow Control Interface signals become available when you turn on Enable MAC Flow Control in the parameter editor.
Signal Name |
Direction |
Description |
---|---|---|
pause_insert_tx0[(FCQN-1):0] pause_insert_tx1[(FCQN-1):0] |
Input | This signal is available if you specify pause on PFC.
The signal indicates to the MAC whether XON or XOFF Pause or PFC flow control frame should be sent.
1-bit mode request model: The IP core ignores pause_insert_tx1[(FCQN-1):0].
The following encoding is defined:
2-bit mode request model: The higher-order bit is in pause_insert_tx1[(FCQN-1):0] and the lower-order bit is in pause_insert_tx0[(FCQN-1):0]. The XON/XOFF request is a level-based request. The following encoding is defined:
|
pause_receive_rx[(FCQN-1):0] | Output | Each pause_receive_rx[(FCQN-1):0] bit indicates the corresponding queue is being paused. This is a level-based signal. |