Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide

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ID 683486
Date 7/12/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency E-Tile 40G Ethernet Intel® FPGA IP 2. Low Latency E-Tile 40G Ethernet IP Core Parameters 3. Getting Started 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. Ethernet Toolkit Overview 10. Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide Archives 11. Comparison Between Low Latency E-Tile 40G Ethernet Core and Low Latency 40GbE IP Core 12. Document Revision History for Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide
1. About the Low Latency E-Tile 40G Ethernet Intel® FPGA IP x
1.1. Release Information 1.2. Low Latency E-Tile 40G Ethernet Intel® FPGA IP Supported Features 1.3. Low Latency E-Tile 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support 1.4. Resource Utilization
1.3. Low Latency E-Tile 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support x
1.3.1. Device Family Support 1.3.2. Low Latency E-Tile 40G Ethernet Intel® FPGA IP Device Speed Grade Support
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the Low Latency E-Tile 40G Ethernet IP Core Parameters and Options 3.3. Simulating the IP Core 3.4. Generated File Structure 3.5. Integrating Your IP Core in Your Design 3.6. Low Latency E-Tile 40G Ethernet IP Core Testbench 3.7. Compiling the Full Design and Programming the FPGA
3.5. Integrating Your IP Core in Your Design x
3.5.1. Pin Assignments 3.5.2. Ethernet Adaptation Flow 3.5.3. Placement Settings for the Low Latency E-Tile 40G Ethernet Core
3.6. Low Latency E-Tile 40G Ethernet IP Core Testbench x
3.6.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Low Latency E-Tile 40G Ethernet Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. Low Latency E-Tile 40G Ethernet Core Functional Description x
4.1.1. Low Latency E-Tile 40G Ethernet Core TX MAC Datapath 4.1.2. Low Latency E-Tile 40G Ethernet Core RX MAC Datapath 4.1.3. Link Fault Signaling Interface 4.1.4. Flow Control
4.1.1. Low Latency E-Tile 40G Ethernet Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC-32) Insertion
4.1.2. Low Latency E-Tile 40G Ethernet Core RX MAC Datapath x
4.1.2.1. IP Core Preamble Processing 4.1.2.2. IP Core Strict SFD Checking 4.1.2.3. Length/Type Field Processing 4.1.2.4. RX CRC Checking and Dynamic Forwarding
4.1.2.3. Length/Type Field Processing x
4.1.2.3.1. Length Checking
4.1.4. Flow Control x
4.1.4.1. TX Pause/PFC Flow Control Transmission 4.1.4.2. XON/XOFF Pause Frames
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers Signals 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals 6.8. Clocks 6.9. Flow Control Interface
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers
9. Ethernet Toolkit Overview x
9.1. Features
1. About the Low Latency E-Tile 40G Ethernet Intel® FPGA IP
2. Low Latency E-Tile 40G Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide Archives
11. Comparison Between Low Latency E-Tile 40G Ethernet Core and Low Latency 40GbE IP Core
12. Document Revision History for Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide

11. Comparison Between Low Latency E-Tile 40G Ethernet Core and Low Latency 40GbE IP Core

Table 29.  Comparison Between the Low Latency E-Tile 40G Ethernet Core and the Low Latency 40G Ethernet Intel® FPGA IP Core
The comparison is defined relative to these versions:
  • Low Latency E-Tile 40G Ethernet IP core available with the Quartus® Prime Pro Edition software release v20.1.
  • Low Latency 40G Ethernet Intel® FPGA IP core available with the Quartus Prime Pro 17.1 Stratix 10 ES Editions software.
This table does not list individual signal name and register differences.

Property

Low Latency E-Tile 40G Ethernet IP Core

Low Latency 40G Ethernet Intel FPGA IP Core

Transceiver tile support

 E-tile L-tile, H-tile

Device support

Supports Stratix® 10 and Agilex™ 7 device family.

Supports Stratix® 10 device family.

Reset

Provides three asynchronous hard reset signals (general, receiver only, and transmitter only) and three soft reset register bits.

Provides three asynchronous hard reset signals (general, receiver only, and transmitter only) and three soft reset register bits.

Client interface width

Avalon® streaming interface 128-bit data bus

Avalon® streaming interface 128-bit data bus

Avalon® streaming transmitter interface readyLatency Avalon® streaming transmitter interface readyLatency configurable at 0 or 3 (parameter). Avalon® streaming transmitter interface readyLatency configurable at 0 or 3 (parameter).
Preamble passthrough Available as a configuration option (parameter). When preamble passthrough is turned on, you must provide the preamble on a separate bus, l2_tx_preamble[63:0], and the IP core provides the RX preamble on a separate bus, l2_rx_preamble[63:0]. Available as a configuration option (parameter). When preamble passthrough is turned on, you must provide the preamble on a separate bus, l2_tx_preamble[63:0], and the IP core provides the RX preamble on a separate bus, l2_rx_preamble[63:0].
Interface to transceiver TX PLL Not required. You must instantiate a single TX PLL IP core to connect to the single tx_serial_clk input pin of the Low Latency 40G Ethernet Intel® FPGA IP core.
Statistics counters Available as a configuration option (parameter). Available as a configuration option (parameter).
Statistics counter increment vectors l2_txstatus_data, l2_txstatus_error, and l2_rxstatus_data signals available on client interface, whether or not statistics registers are enabled. l2_txstatus_data, l2_txstatus_error, and l2_rxstatus_data signals available on client interface, whether or not statistics registers are enabled.
40GBASE-KR4 Not supported. Available as a configuration option. Configurable support for 40GBASE-KR4 or 40GBASE-CR4. Implements the IEEE Backplane Ethernet Standard 802.3-2012.
Flow control Available as a configuration option (parameter). Available as a configuration option (parameter).
1588 PTP support Not supported. Not supported.
Enable alignment of EOP on FCS word Always turned on. Always turned on.
Minimum average interpacket gap Value is 12 bytes. Value is 12 bytes.
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