AN 720: Simulating the ASMI Block in Your Design

ID 683464
Date 7/29/2020
Public

1.2.3. WYSIWYG for ASMI Block

If you want to use ASMI in user mode, then you must instantiate the WYSIWYG (What You See Is What You Get) of the ASMI block in your design. Instantiating the WYSIWYG of the ASMI block in your design allows you to access the active serial pins from the FPGA user design.

Example of Verilog WYSIWYG for Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V ASMI Block

<device>_asmiblock <name>
(
	.dclk(<clock source from user design>),
	.sce(<1 bit SCE from user design>),
	.oe(<output enable from user design>),
	.data0out(<AS_DATA0 from user design>),
	.data1out(<AS_DATA1 from user design>),
	.data2out(<AS_DATA2 from user design>),
	.data3out(<AS_DATA3 from user design>),

	.data0oe (<OE of data0out from user design>),
	.data1oe (<OE of data1out from user design>),
	.data2oe (<OE of data2out from user design>),
	.data3oe (<OE of data3out from user design>),

	.data0in(<AS_DATA0 to user design>),
	.data1in(<AS_DATA1 to user design>),
	.data2in(<AS_DATA2 to user design>),
	.data3in(<AS_DATA3 to user design>)
);
defparam <name>.enable_sim = "false";

Example of VHDL WYSIWYG for Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V ASMI Block

component <device>_asmiblock
    generic(
      enable_sim :     string    :=  "false"
    );
    port(
        dclk     :    in    std_logic;
        sce      :    in    std_logic;
        oe       :    in    std_logic;
        data0out :    in    std_logic;
        data1out :    in    std_logic;
        data2out :    in    std_logic;
        data3out :    in    std_logic;
        data0oe  :    in    std_logic;
        data1oe  :    in    std_logic;
        data2oe  :    in    std_logic;
        data3oe  :    in    std_logic;
        data0in  :    out  std_logic;
        data1in  :    out  std_logic;
        data2in  :    out  std_logic;
        data3in  :    out  std_logic
    );
  end component;

Example of Verilog WYSIWYG for Intel® Arria® 10 ASMI Block

<device>_asmiblock <name>
(
	.dclk(<clock source from user design>),
	.sce(<3 bit SCE from user design>),
	.oe(<output enable from user design>),
	.data0out(<AS_DATA0 from user design>),
	.data1out(<AS_DATA1 from user design>),
	.data2out(<AS_DATA2 from user design>),
	.data3out(<AS_DATA3 from user design>),

	.data0oe (<OE of data0out from user design>),
	.data1oe (<OE of data1out from user design>),
	.data2oe (<OE of data2out from user design>),
	.data3oe (<OE of data3out from user design>),

	.data0in(<AS_DATA0 to user design>),
	.data1in(<AS_DATA1 to user design>),
	.data2in(<AS_DATA2 to user design>),
	.data3in(<AS_DATA3 to user design>)
);
defparam <name>.enable_sim = "false";

Example of VHDL WYSIWYG for Intel® Arria® 10 ASMI Block

component <device>_asmiblock
    generic(
      enable_sim :     string    :=  "false"
    );
    port(
        dclk     :    in    std_logic;
        sce      :    in    std_logic_vector(2 downto 0);
        oe       :    in    std_logic;
        data0out :    in    std_logic;
        data1out :    in    std_logic;
        data2out :    in    std_logic;
        data3out :    in    std_logic;
        data0oe  :    in    std_logic;
        data1oe  :    in    std_logic;
        data2oe  :    in    std_logic;
        data3oe  :    in    std_logic;
        data0in  :    out  std_logic;
        data1in  :    out  std_logic;
        data2in  :    out  std_logic;
        data3in  :    out  std_logic
    );
  end component;

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