Intel® Quartus® Prime Pro Edition User Guide: Getting Started

ID 683463
Date 10/04/2021
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2.11. Managing Projects Revision History

Document Version Intel® Quartus® Prime Version Changes
2021.06.21 21.2
  • Added Version-Compatible Compilation Database Support table.
  • Added "Promoting Critical Warnings to Errors" topic.
2021.03.29 21.1
  • Added "Creating Database-Only Archives" topic.
  • Added "Promoting Critical Warnings to Errors" topic
2020.09.28 20.3
  • Updated "Back-Annotate Optimized Assignments" for support of pins, clocks, RAMs, and DSPs.
2020.05.01 20.1
  • Added note about .qar file requirements to "Design Guidelines for Component Instances" topic.
2019.09.30 19.3
  • Added "Disabling Automated Problem Reports" topic.
  • Added "Suppressing Messages" topic.
2018.09.24 18.1
  • Subdivided "Exporting, Archiving, and Migrating Projects" into separate sections.
  • Described migration of full chip database in "Exporting a Version-Compatible Compilation Database" topic.
  • Described automated .qdb partition export in "Exporting a Design Partition" topic.
  • Added "Viewing Quartus Database File Information" topic.
  • Added "Specifying the Target Device or Board" topic.
  • Divided "Introduction to Intel FPGA IP Cores" into separate chapter.
  • Moved "IP Core Best Practices" topic to Introduction to Intel FPGA IP Cores chapter.
  • Moved "Factors Affecting Compilation Results" topic to Design Compilation: Intel Quartus Prime Pro Edition User Guide.
2018.05.07 18.0.0
  • Initial release as chapter of Getting Started User Guide.
  • Revised "Exporting a Design Partition" topic to add Include entity-bound SDC files for the selected partition option, to add prerequisite steps, and to remove import step covered in separate topic.
  • Changed title of "Managing Team-Based Designs" to "Exporting, Archiving, and Migrating Projects" and updated content.
  • Changed title of "Migrating Compilation Results Across Software Versions" to "Exporting the Compilation Database" and updated content.
  • Changed title of "Exporting the Results Database" to "Exporting a Version-Compatible Design Compilation Database" and updated content.
  • Changed title of "Importing the Results Database" to "Importing a Version-Compatible Design Compilation Database" and updated content.
  • Changed title of "Cleaning the Project Database" to "Cleaning the Project Compilation Database."
  • Updated screenshots of IP Catalog and Parameter Editor for latest IP names.
Date Version Changes
2017.11.06 17.1.0
  • Revised product branding for Intel® standards.
  • Revised topics on Intel® FPGA IP Evaluation Mode (formerly OpenCore).
  • Removed -compatible attribute from export_design command content.
  • Updated figure: IP Upgrade Alert in Project Navigator.
  • Updated IP Core Upgrade Status table with new icons, and added row for IP Component Outdated status.
2017.05.08 17.0.0
  • Added Project Tasks pane and update New Project Wizard.
  • Updated Compilation Dashboard image to show concurrent analysis.
  • Removed Smart Compilation option from Settings dialog box screenshot.
  • Updated IP Catalog screenshots for latest GUIs.
  • Added topic on Back-Annotate Assignments command.
  • Added Exporting a Design Partition topic.
  • Removed mentions to deprecated Incremental Compilation.
  • Added reference to Block-Level Design Flows.
2016.10.31 16.1.0
  • Added references to compilation stages and snapshots.
  • Removed support for comparing revisions.
  • Added references to .ip file creation during Intel® Quartus® Prime Pro Edition stand-alone IP generation.
  • Updated IP Core Generation Output files list and diagram.
  • Added Support for IP Core Encryption topic.
  • Rebranding for Intel
2016.05.03 16.0.0
  • Removed statements about serial equivalence when using multiple processors.
  • Added the "Preserving Compilation Results" section.
  • Added the "Migrating Results Across Quartus Prime Software" section and its subsections for information about importing and exporting compilation results between different versions of Quartus Prime.
  • Added the "Project Database Commands" section and its subsections.
2016.02.09 15.1.1
  • Clarified instructions for Generating a Combined Simulator Setup Script.
  • Clarified location of Save project output files in specified directory option.
2015.11.02 15.1.0
  • Added Generating Version-Independent IP Simulation Scripts topic.
  • Added example IP simulation script templates for supported simulators.
  • Added Incorporating IP Simulation Scripts in Top-Level Scripts topic.
  • Added Troubleshooting IP Upgrade topic.
  • Updated IP Catalog and parameter editor descriptions for GUI changes.
  • Updated IP upgrade and migration steps for latest GUI changes.
  • Updated Generating IP Cores process for GUI changes.
  • Updated Files Generated for IP Cores and Qsys system description.
  • Removed references to devices and features not supported in version 15.1.
  • Changed instances of Quartus II to Intel® Quartus® Prime .
2015.05.04 15.0.0
  • Added description of design templates feature.
  • Updated screenshot for DSE II GUI.
  • Added qsys_script IP core instantiation information.
  • Described changes to generating and processing of instance and entity names.
  • Added description of upgrading IP cores at the command line.
  • Updated procedures for upgrading and migrating IP cores.
  • Gate level timing simulation supported only for Cyclone IV and Stratix IV devices.
2014.12.15 14.1.0
  • Updated content for DSE II GUI and optimizations.
  • Added information about new Assignments > Settings > IP Settings that control frequency of synthesis file regeneration and automatic addition of IP files to the project.
2014.08.18

14.0a10.0

  • Added information about specifying parameters for IP cores targeting Arria 10 devices.
  • Added information about the latest IP output for version 14.0a10 targeting Arria 10 devices.
  • Added information about individual migration of IP cores to the latest devices.
  • Added information about editing existing IP variations.
2014.06.30 14.0.0
  • Replaced MegaWizard Plug-In Manager information with IP Catalog.
  • Added standard information about upgrading IP cores.
  • Added standard installation and licensing information.
  • Removed outdated device support level information. IP core device support is now available in IP Catalog and parameter editor.
November 2013 13.1.0
  • Conversion to DITA format
May 2013 13.0.0
  • Overhaul for improved usability and updated information.
June 2012 12.0.0
  • Removed survey link.
  • Updated information about VERILOG_INCLUDE_FILE.
November 2011 10.1.1 Template update.
December 2010 10.1.0
  • Changed to new document template.
  • Removed Figure 4–1, Figure 4–6, Table 4–2.
  • Moved “Hiding Messages” to Help.
  • Removed references about the set_user_option command.
  • Removed Classic Timing Analyzer references.