Intel® High Level Synthesis Compiler Pro Edition: User Guide

ID 683456
Date 6/20/2022
Public

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5. Optimizing and Refining Your Component

After you have verified the functionality of your component and testbench, you can compile your component to RTL and review the High-Level Design Reports to further optimize and refine your component design. The High-Level Design Reports show estimates of various aspects of how your component will be implemented in hardware.

By compiling your component to RTL and reviewing the High-Level Design Reports, you can see how your code changes affect your component hardware implementation without needing to run a simulation or a full Quartus compilation.
To compile your component to RTL without running a simulation, issue the following command:
i++ -march="<FPGA_family_or_part_number>" --simulator none

You can also compile your component with a Questa* simulation flow by omitting the --simulator none option. Compiling without a simulation test bench is faster, but you cannot simulate your design to measure its latency and generate waveforms.

To view the High-Level Design Reports, open the following file in a web browser:
<result>.prj/reports/report.html

For information about techniques that you can apply to optimize and refine your component, see Intel® High Level Synthesis Compiler Pro Edition Best Practices Guide .

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