ID 683456
Date 6/20/2022
Public

## 6.2. Debugging during Verification

By default, the HLS compiler instructs the simulator not to log any signals because logging signals slows the simulation, and the waveforms files can be very large. However, you can configure the compiler to save these waveforms for debugging purposes.

To enable signal logging in the simulator, invoke the i++ command with the -ghdl option in your i++ command, as follows:
i++ -march="<FPGA_family_or_part_number>" -ghdl[=<depth>] <input files>
Specify the <depth> attribute to specify how many levels of hierarchy are logged. Specify -ghdl=1 to log only top level signals. If you do not specify the <depth> attribute, all signals are logged.
Remember: After you compile your component and testbench with the -ghdl option, run the resulting executable to run the simulation and generate the waveform. By default, the name of the executable is a.out (Linux) or a.exe (Windows).

When the simulation finishes, open the vsim.wlf file inside the <result>.prj/verification directory to view the waveform.

To view the waveform after the simulation finishes:

1. In Questa®, open the vsim.wlf file inside the <result>.prj/verification directory.
2. Right-click the <component_name>_inst block and select Add Wave.

You can now view the component top-level signals: start, busy, stall, done, parameters, and outputs. Use the waveform to see how the component interacts with its interfaces.

Tip:

When you view the simulation waveform in Questa®, the simulation clock period is set to a default value of 1000 picoseconds (ps). To synchronize the Time axis to show one cycle per tick mark, change the time resolution from picoseconds (ps) to nanoseconds (ns):

1. Right-click the timeline and select Grid, Timeline & Cursor Control.
2. Under Timeline Configuration, set the Time units to ns.