1. Intel® High Level Synthesis Compiler Pro Edition User Guide 2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition 3. Creating a High-Level Synthesis Component and Testbench 4. Verifying the Functionality of Your Design 5. Optimizing and Refining Your Component 6. Verifying Your IP with Simulation 7. Synthesize your Component IP with Intel® Quartus® Prime Pro Edition 8. Integrating your IP into a System A. Reviewing the High-Level Design Reports (report.html) B. Intel® HLS Compiler Pro Edition Restrictions C. Intel® HLS Compiler Pro Edition User Guide Archives D. Document Revision History for Intel® HLS Compiler Pro Edition User Guide
6.1. Generation of the Verification Testbench Executable
When you include -march="<FPGA_family_or_part_number>" in your i++ command, the HLS compiler identifies the components and performs high-level synthesis on them. It then generates an executable to run a verification testbench.
The HLS compiler performs the following tasks to generate the verification executable:
- Parses your design, and extracts the functions and symbols necessary for component synthesis to the FPGA. The HLS compiler also extracts the functions and symbols necessary for compiling the C++ testbench.
- Compiles the testbench code to generate an x86-64 executable that also runs the simulator.
- Compiles the code for component synthesis to the FPGA. This compilation generates RTL for the component and an interface to the x86-64 executable testbench.
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