5. Optimizing and Refining Your Component
After you have verified the functionality of your component and testbench, you can compile your component to RTL and review the High-Level Design Reports to further optimize and refine your component design. The High-Level Design Reports show estimates of various aspects of how your component will be implemented in hardware.
i++ -march="<FPGA_family_or_part_number>" --simulator none
You can also compile your component with a Questa* simulation flow by omitting the --simulator none option. Compiling without a simulation test bench is faster, but you cannot simulate your design to measure its latency and generate waveforms.
For information about techniques that you can apply to optimize and refine your component, see Intel® High Level Synthesis Compiler Pro Edition Best Practices Guide .
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