Intel® FPGA Power and Thermal Calculator User Guide

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ID 683445
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. Overview of the Intel® FPGA Power and Thermal Calculator 2. Setting Up the Intel® FPGA Power and Thermal Calculator 3. Intel® FPGA Power and Thermal Calculator Graphical User Interface 4. Intel® FPGA Power and Thermal Calculator Pages 5. Factors Affecting the Accuracy of the Intel® FPGA Power and Thermal Calculator 6. Intel® FPGA Power and Thermal Calculator User Guide Archive 7. Document Revision History for the Intel® FPGA Power and Thermal Calculator User Guide A. Measuring Static Power
1. Overview of the Intel® FPGA Power and Thermal Calculator x
1.1. Intel® FPGA PTC Power Model Status 1.2. Definitions of Power Terms Used in this Document
2. Setting Up the Intel® FPGA Power and Thermal Calculator x
2.1. Availability 2.2. Obtaining the Standalone Intel® FPGA Power and Thermal Calculator 2.3. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator 2.4. Power Analysis for Dual-Core 1SG10M Intel® Stratix® 10 Devices
2.3. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator x
2.3.1. Estimating Power Consumption Before Starting the FPGA Design 2.3.2. Estimating Power Consumption While Creating the FPGA Design 2.3.3. Estimating Power Consumption After Completing the FPGA Design
3. Intel® FPGA Power and Thermal Calculator Graphical User Interface x
3.1. Intel® FPGA PTC Select Family Dialog Box 3.2. Intel® FPGA PTC Basic GUI Components
3.2. Intel® FPGA PTC Basic GUI Components x
3.2.1. Intel® FPGA PTC Data Entry Pages 3.2.2. Intel® FPGA PTC Field Types 3.2.3. Intel® FPGA PTC Input Field Dependencies 3.2.4. Intel® FPGA PTC Data Entry Error Messages
4. Intel® FPGA Power and Thermal Calculator Pages x
4.1. Intel® FPGA PTC - Power Summary 4.2. Intel® FPGA PTC - Common Page Elements 4.3. Intel® FPGA PTC - Device Selection and Thermal Analysis Windows 4.4. Intel® FPGA PTC - Main Page 4.5. Intel® FPGA PTC - Logic Page 4.6. Intel® FPGA PTC - RAM Page 4.7. Intel® FPGA PTC - DSP Page 4.8. Intel® FPGA PTC - Clock Page 4.9. Intel® FPGA PTC - PLL Page 4.10. Intel® FPGA PTC - I/O Page 4.11. Intel® FPGA PTC - I/O-IP Page 4.12. Intel® FPGA PTC - Transceiver Page 4.13. Intel® FPGA PTC - HPS Page 4.14. Intel® FPGA PTC - HBM Page ( Intel® Stratix® 10 Devices Only) 4.15. Intel® FPGA PTC - Thermal Page 4.16. Intel® FPGA PTC - Report Page
4.12. Intel® FPGA PTC - Transceiver Page x
4.12.1. Estimating E-Tile Channel PLL Power with the Intel Power and Thermal Calculator
5. Factors Affecting the Accuracy of the Intel® FPGA Power and Thermal Calculator x
5.1. Toggle Rate 5.2. I/O Bank Allocation
1. Overview of the Intel® FPGA Power and Thermal Calculator
2. Setting Up the Intel® FPGA Power and Thermal Calculator
3. Intel® FPGA Power and Thermal Calculator Graphical User Interface
4. Intel® FPGA Power and Thermal Calculator Pages
5. Factors Affecting the Accuracy of the Intel® FPGA Power and Thermal Calculator
6. Intel® FPGA Power and Thermal Calculator User Guide Archive
7. Document Revision History for the Intel® FPGA Power and Thermal Calculator User Guide
A. Measuring Static Power

4.1. Intel® FPGA PTC - Power Summary

The Power Summary tile of the Intel® FPGA Power and Thermal Calculator ( Intel® FPGA PTC) can be displayed at all times, and shows the calculated power consumption by resource type.

The values displayed in the Power Summary update in real time as you change parameters on the data entry pages.

In addition to displaying total power consumption, the Power Summary displays power consumption for the resource types listed in the following table.

Table 3.  Resource Types Displayed in the Power Summary
Intel® Agilex™ PTC Power Summary
Resource Type Description
Logic The dynamic power consumed by adaptive logic modules (ALMs), flipflops (FFs) and routing fabric.
RAM The dynamic power consumed by specialized blocks optimized for data storage and retrieval.
DSP The dynamic power consumed by specialized blocks optimized for fast math operations.
Clock The dynamic power consumed by clock networks. The clock dynamic power is affected by the selected device.
PLL The dynamic power consumed by phase-locked loops (PLLs).
I/O The dynamic power consumed by I/O pins and I/O subsystems.
Transceiver The dynamic power consumed by transceiver blocks.
HPS The dynamic power consumed by the hard processor system (HPS).
HBM The dynamic power consumed by high-bandwidth memory (HBM) and the universal interface bus (UIB) modules.
Static Power The power that the configured device consumes when powered up but with no user clocks operating. The static power (PSTATIC) is the power dissipated on the chip, independent of design activity. PSTATIC includes the static power from all FPGA functional blocks. PSTATIC varies with junction temperature and power characteristics (process). PSTATIC is also the only power component that varies significantly with selected device.
Static Power Savings The package static power savings that occur in standard operation mode. Includes the static power reduction that occurs when not all power rails are at their maximum simultaneously.
SmartVID Power Savings The total power reduction (static and dynamic) resulting from the lower voltage that is made possible by SmartVID. This power reduction is dependent on the user design and device characteristics. The combination of these factors may result in different static and dynamic power savings, so the exact dynamic and static components are not identified separately, and the power reduction reported here is a worst-case result. The reduction reported in this field is already taken into consideration in the Total Power (W) field. The SmartVID Power Savings field applies only to devices that support SmartVID and only when Power Characteristics is set to Maximum.
Total Power The total power dissipated as heat from the FPGA. Does not include power dissipated in off-chip termination resistors. Total power dissipation in the FPGA may differ from the sum of power on all rails due to several factors including, but not limited to, power dissipated in off-chip termination resistors.
Intel® Stratix® 10 PTC Power Summary
Resource Type Description
Logic The dynamic power consumed by adaptive logic modules (ALMs), flipflops (FFs) and associated routing.
RAM The dynamic power consumed by RAMs and associated routing.
DSP The dynamic power consumed by digital signal processing (DSP) blocks and associated routing.
Clock The dynamic power consumed by clock networks. The clock dynamic power is affected by the selected device.
PLL The dynamic and standby power consumed by phase-locked loops (PLLs).
I/O The dynamic and standby power consumed by I/O pins and I/O subsystems.
Transceiver The dynamic and standby power consumed by transceiver blocks.
Hard Processor The dynamic and standby power consumed by the hard processor system (HPS).
High-Bandwidth Memory The dynamic power consumed by high-bandwidth memory (HBM) and the universal interface bus (UIB) modules.
Static Power The static power consumed regardless of clock frequency. This includes static power consumed by I/O and transceiver blocks, but does not include standby power.
Total, Before SmartVID Savings The total power consumption before SmartVID power savings. Includes static power (PSTATIC) and power consumed by different blocks as reported above. Does not include power dissipated in off-chip termination resistors.
SmartVID Savings The total power reduction (static and dynamic) resulting from the lower voltage that is made possible by SmartVID. This power reduction is dependent on the user design and device characteristics. The combination of these factors may result in different static and dynamic power savings, so the exact dynamic and static components are not identified separately, and the power reduction reported here is a worst-case result. The reduction reported in this field is already taken into consideration in the Total (W) field. The SmartVID Power Savings field applies only to devices that support SmartVID and only when Power Characteristics is set to Maximum.
Total Power The total power dissipated as heat from the FPGA. Does not include power dissipated in off-chip termination resistors. Total power dissipation in the FPGA may differ from the sum of power on all rails due to several factors including, but not limited to, power dissipated in off-chip termination resistors.
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