4.11. Intel® FPGA PTC - I/O-IP Page
Analog I/O power and digital power of hard memory controllers and HPS IPs entered on this page are reported in the Analog Power and Digital Power fields of the I/O page. If the IP uses other resource types (for example Logic or PLL), the power is reported on the corresponding page.
I/O-IP Page Information
|Module||Specifies a name for the IP in this column. The module name depends on the selected IP type. It helps to cross-reference each IP module and its corresponding auto-populated entries on other pages. This name is auto-populated when IP type is selected in the IP column and cannot be changed.|
|IP||Specifies the type of the IP in the design.|
|Voltage||Specifies the I/O voltage of the signaling between periphery device and interface.|
|Data Width (Bits)||Specifies the interface data width of the specific IP (in bits).|
|# of DQS Groups||Specifies the number of DQS groups.|
|Memory Device(s)||Specifies the number of memory devices connected to the interface.|
|Total Address Width||Specifies the total address width. This value is used to derive the total number of address pins required.|
|DDR Rate||Specifies the clock rate of user logic. Determines the clock frequency of user logic in relation to the memory clock frequency. For example, if the memory clock sent from the FPGA to the memory device is toggling at 800MHz, a "Quarter rate" interface means that the user logic in the FPGA runs at 200MHz.|
|PHY Rate||Specifies the clock rate of PHY logic. Determines the clock frequency of PHY logic in relation to the memory clock frequency. For example, if the memory clock sent from the FPGA to the memory device is toggling at 800MHz, a "Quarter rate" interface means that the PHY logic in the FPGA runs at 200MHz.|
|Memory Clock Frequency (MHz)||Specifies the frequency of memory clock (in MHz).|
|PLL Reference Clock Frequency (MHz)||Reports the PLL Reference Clock Frequency (in MHz).|
|User Comments||Enter any comments. This is an optional entry.|
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