Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines

ID 683417
Date 10/29/2021

Reference Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 8.  Reference Pins
Pin Name Pin Functions Pin Description Connection Guidelines
RZQ_[#] I/O Reference pins for I/O banks. The RZQ pins share the same VCCIO with the I/O bank where they are located. Connect the external precision resistor to the designated pin within the bank. If not required, this pin is a regular I/O pin.

When using OCT tie these pins to GND through either a 240-Ω or 100-Ω resistor, depending on the desired OCT impedance. Refer to the Intel® Cyclone® 10 GX Device Handbook for the OCT impedance options for the desired OCT scheme.

DNU Do Not Use Do Not Use (DNU). Do not connect to power, GND, or any other signal. These pins must be left floating.
NC No Connect Do not drive signals into these pins.

When designing for device migration, you have the option to connect these pins to either power, GND, or a signal trace depending on the pin assignment of the devices selected for migration.

However, if device migration is not a concern, leave these pins floating.