Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines

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ID 683417
Date 10/29/2021
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Document Table of Contents x
Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines
Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines x
Intel® Cyclone® 10 GX Pin Connection Guidelines Power Supply Sharing Guidelines for Intel® Cyclone® 10 GX Devices Document Revision History for the Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines
Intel® Cyclone® 10 GX Pin Connection Guidelines x
Clock and PLL Pins Dedicated Configuration/JTAG Pins Optional/Dual-Purpose Configuration Pins 3V Compatible I/O Pins Differential I/O Pins External Memory Interface Pins Voltage Sensor Pins Reference Pins Supply Pins Transceiver Pins Notes to Intel® Cyclone® 10 GX Pin Connection Guidelines
Power Supply Sharing Guidelines for Intel® Cyclone® 10 GX Devices x
Example 1— Intel® Cyclone® 10 GX Example 2— Intel® Cyclone® 10 GX
Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines

External Memory Interface Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 6.  External Memory Interface Pins
Pin Name Pin Functions Pin Description Connection Guidelines
DQS[#] I/O,bi-directional Optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry. Connect unused pins as defined in the Intel® Quartus® Prime software.
DQSn[#] I/O,bi-directional Optional complementary data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry. Connect unused pins as defined in the Intel® Quartus® Prime software.
DQ[#] I/O,bi-directional Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is not important. However, if you plan on migrating to a different memory interface that has a different DQ bus width, you will need to reevaluate your pin assignments. Analyze the available DQ pins across all pertinent DQS columns in the pin list. Connect unused pins as defined in the Intel® Quartus® Prime software.
DQS[#]_[#] I/O, bidirectional Optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry. The shifted DQS signal can also drive to internal logic. Connect unused pins as defined in the Intel® Quartus® Prime software.
DQSn[#]_[#] I/O, bidirectional Optional complementary data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry. Connect unused pins as defined in the Intel® Quartus® Prime software.
DQ[#]_[#]_[#] I/O, bidirectional Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is not important. However, if you plan on migrating to a different memory interface that has a different DQ bus width, you will need to reevaluate your pin assignments. Analyze the available DQ pins across all pertinent DQS columns in the pin list. Connect unused pins as defined in the Intel® Quartus® Prime software.
DM[#]_[#] I/O, Output Optional write data mask, edge-aligned to DQ during write. Connect unused pins as defined in the Intel® Quartus® Prime software.
RESET_N_0 I/O, Output Active low reset signal. Connect unused pins as defined in the Intel® Quartus® Prime software.
A_[#] I/O, Output Address input for DDR3 SDRAM. Connect unused pins as defined in the Intel® Quartus® Prime software.
BA_[#] I/O, Output Bank address input for DDR3 SDRAM. Connect unused pins as defined in the Intel® Quartus® Prime software.
CK_[#] I/O, Output Input clock for external memory devices. Connect unused pins as defined in the Intel® Quartus® Prime software.
CK_N_[#] I/O, Output Input clock for external memory devices, inverted CK. Connect unused pins as defined in the Intel® Quartus® Prime software.
CKE_[#] I/O, Output High signal enables clock, low signal disables clock. Connect unused pins as defined in the Intel® Quartus® Prime software.
CS_N_[#] I/O, Output Active low chip select. Connect unused pins as defined in the Intel® Quartus® Prime software.
CA_[#]_[#] I/O, Output Command and address input for LPDDR3 SDRAM. Connect unused pins as defined in the Intel® Quartus® Prime software.
ODT_[#] I/O, Output On die termination signal to set the termination resistors to each pin. Connect unused pins as defined in the Intel® Quartus® Prime software.
WE_N_0 I/O, Output Write-enable input for DDR3 SDRAM and all supported protocols. Connect unused pins as defined in the Intel® Quartus® Prime software.
CAS_N_0 I/O, Output Column address strobe for DDR3 SDRAM. Connect unused pins as defined in the Intel® Quartus® Prime software.
RAS_N_0 I/O, Output Row address strobe for DDR3 SDRAM. Connect unused pins as defined in the Intel® Quartus® Prime software.
ALERT_N_0 I/O, Input Alert input that indicate to the system's memory controller that a specific alert or event has occurred.

Connect unused pins as defined in the Intel® Quartus® Prime software.

PAR_0 I/O, Output Command and Address Parity Output. Connect unused pins as defined in the Intel® Quartus® Prime software.
CFG_N_0 I/O, Output Configuration bit. Connect unused pins as defined in the Intel® Quartus® Prime software.
LBK[#]_N_0 I/O, Output Loop-back mode. Connect unused pins as defined in the Intel® Quartus® Prime software.
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