1.3.2. Receiver Transport Layer
To check the data integrity of the payload data stream through the RX JESD204B IP core and transport layer, the ADC is configured to output PRBS-9 test data pattern. The ADC is also set to operate with the same configuration as set in the JESD204B IP core. The PRBS checker in the FPGA fabric checks data integrity for one minute.
Figure shows the conceptual test setup for data integrity checking.
Figure 4. Data Integrity Check Using PRBS Checker
The SignalTap II Logic Analyzer tool is used to monitor the operation of the RX transport layer.
|Test Case||Objective||Description||Passing Criteria|
|TL.1||Check the transport layer mapping.||The following signals in altera_jesd204_transport_rx_top.v are tapped:
M is the number of converters.
The rxframe_clk is used as the SignalTap II sampling clock.
The data_error signal is the PRBS checker's pass or fail indicator.
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