Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report

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ID 683414
Date 6/25/2015
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Document Table of Contents x
1. Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report
1. Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and AD9250 Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization
1. Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report

1.5. Test Results

The following table contains the possible results and their definition.
Table 7.  Results Definition
Result Definition
PASS The Device Under Test (DUT) was observed to exhibit conformant behavior.
PASS with comments The DUT was observed to exhibit conformant behavior. However, an additional explanation of the situation is included, such as due to time limitations, only a portion of the testing was performed.
FAIL The DUT was observed to exhibit non-conformant behavior.
Warning The DUT was observed to exhibit behavior that is not recommended.
Refer to comments From the observations, a valid pass or fail could not be determined. An additional explanation of the situation is included.

The following table shows the results for test cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1 with different values of L, M, F, K, subclass, data rate, sampling clock, link clock and SYSREF frequencies.

Table 8.  Test Results
Test L M F Sub-class SCR K Data rate (Mbps) Sampling Clock (MHz) Link Clock (MHz) SYSREF (MHz) Result
1 1 1 2 0 0 16 4915 245.76 122.88 — PASS
2 1 1 2 0 0 32 4915 245.76 122.88 — PASS
3 1 1 2 0 1 16 4915 245.76 122.88 — PASS
4 1 1 2 0 1 32 4915 245.76 122.88 — PASS
5 1 1 2 1 0 16 4915 245.76 122.88 15.36 PASS
6 1 1 2 1 0 32 4915 245.76 122.88 7.68 PASS
7 6 1 1 2 1 1 16 4915 245.76 122.88 15.36 PASS
8 6 1 1 2 1 1 32 4915 245.76 122.88 7.68 PASS
9 1 2 4 0 0 16 4915 122.88 122.88 — PASS
10 1 2 4 0 0 32 4915 122.88 122.88 — PASS
11 1 2 4 0 1 16 4915 122.88 122.88 — PASS
12 1 2 4 0 1 32 4915 122.88 122.88 — PASS
13 1 2 4 1 0 16 4915 122.88 122.88 7.68 PASS
14 1 2 4 1 0 32 4915 122.88 122.88 3.84 PASS
15 6 1 2 4 1 1 16 4915 122.88 122.88 7.68 PASS
16 6 1 2 4 1 1 32 4915 122.88 122.88 3.84 PASS
17 2 1 1 0 0 20 2457 245.76 61.44 — PASS
18 2 1 1 0 0 32 2457 245.76 61.44 — PASS
19 2 1 1 0 1 20 2457 245.76 61.44 — PASS
20 2 1 1 0 1 32 2457 245.76 61.44 — PASS
21 2 1 1 1 0 20 2457 245.76 61.44 12.288 PASS
22 2 1 1 1 0 32 2457 245.76 61.44 7.68 PASS
23 6 2 1 1 1 1 20 2457 245.76 61.44 12.288 PASS
24 6 2 1 1 1 1 32 2457 245.76 61.44 7.68 PASS
25 2 2 2 0 0 16 4915 245.76 122.88 — PASS
26 2 2 2 0 0 32 4915 245.76 122.88 — PASS
27 2 2 2 0 1 16 4915 245.76 122.88 — PASS
28 2 2 2 0 1 32 4915 245.76 122.88 — PASS
29 2 2 2 1 0 16 4915 245.76 122.88 15.36 PASS
30 2 2 2 1 0 32 4915 245.76 122.88 7.68 PASS
31 6 2 2 2 1 1 16 4915 245.76 122.88 15.36 PASS
32 6 2 2 2 1 1 32 4915 245.76 122.88 7.68 PASS
Table 9.  Deterministic Latency Measurement for Arria V GT
Test L M F Sub-class K Data rate (Mbps) Sampling Clock (MHz) Link Clock (MHz) SYSREF (MHz) Result
DL.1 2 2 2 1 32 4915 245.76 122.88 7.68 PASS
DL.2 2 2 2 1 32 4915 245.76 122.88 7.68 PASS
DL.3 2 2 2 1 32 4915 245.76 122.88 7.68 PASS with comments.

Link clock observed: 131-132

Table 10.  Deterministic Latency Measurement for Arria V SoC
Test L M F Subclass SCR K Data Rate (Msps) Link Clock (MHz) Result
DL.1 1 1 2 1 1 16 4915 122.88 PASS
DL.2 PASS
DL.3 PASS with comments.

Link clock observed: 83

DL.1 1 1 2 1 1 32 4915 122.88 PASS
DL.2 PASS
DL.3 PASS with comments.

Link clock observed: 131

DL.1 1 2 4 1 1 16 4915 122.88 PASS
DL.2 PASS
DL.3 PASS with comments.

Link clock observed: 131

DL.1 1 2 4 1 1 32 4915 122.88 PASS
DL.2 PASS
DL.3 PASS with comments.

Link clock observed: 227

DL.1 2 1 1 1 1 20 2457 61.44 PASS
DL.2 PASS
DL.3 PASS with comments.

Link clock observed: 63

DL.1 2 1 1 1 1 32 2457 61.44 PASS
DL.2 PASS
DL.3 PASS with comments.

Link clock observed: 83

DL.1 2 2 2 1 1 16 4915 122.88 PASS
DL.2 PASS
DL.3 PASS with comments.

Link clock observed: 83

DL.1 2 2 2 1 1 32 4915 122.88 PASS
DL.2 PASS
DL.3 PASS with comments.

Link clock observed: 131

The following figure shows the SignalTap II waveform of the clock count from the deassertion of SYNC~ in the first output of the ramp test pattern. The clock count measures the first user data output latency.

Figure 7.  Deterministic Latency Measurement Ramp Test Pattern


6 Results for both Arria V GT and Arria V SoC devices.
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