L/H-tile Hard IP for PCI Express* IP Core Release Notes

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ID 683412
Date 12/13/2021
Public
Document Table of Contents
Document Table of Contents x
1. L/H-tile Hard IP for PCI Express* IP Core Release Notes
1. L/H-tile Hard IP for PCI Express* IP Core Release Notes x
1.1. L/H-tile Hard IP for PCI Express* IP Cores for 21.4 1.2. L/H-tile Hard IP for PCI Express* IP Cores for 21.3 1.3. L/H-tile Hard IP for PCI Express IP Core v20.4 1.4. L/H-tile Hard IP for PCI Express* IP Core v19.3 1.5. L/H-tile Hard IP for PCI Express* IP Core v19.1 1.6. L/H-tile Hard IP for PCI Express* IP Core v18.1.1 1.7. L/H-tile Hard IP for PCI Express* IP Core v18.0 1.8. L/H-tile Hard IP for PCI Express* IP Core v17.1
1.2. L/H-tile Hard IP for PCI Express* IP Cores for 21.3 x
1.2.1. L/H-tile Avalon® Streaming Hard IP for PCI Express* IP Core v23.0.0 1.2.2. L/H-tile Avalon® Memory-mapped Hard IP for PCI Express* IP Core v22.2.0
1. L/H-tile Hard IP for PCI Express* IP Core Release Notes

1.2.1. L/H-tile Avalon® Streaming Hard IP for PCI Express* IP Core v23.0.0

Table 2.  v23.0.0 2021.10.04
Intel® Quartus® Prime Version Description Impact
21.3 The L/H-tile Avalon® Streaming IP for PCIe reinstated the IOPLL-based clock tree (same as in 20.4) while moving away from a clock divider-based clock tree to ensure robust clock and reset handling. Since this is a major revision, you must regenerate your L/H-tile Avalon® Streaming IP for PCIe when migrating your design to 21.3.
Removed duplicate Link port number (Root Port only) parameters from the Parameter Editor of the L/H-tile Avalon® Streaming Hard IP for PCI Express* IP. You will automatically get this enhancement when you regenerate your L/H-tile Avalon® Streaming IP for PCIe when migrating your design to 21.3.
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