1.5. L/H-tile Hard IP for PCI Express* IP Core v19.1
Description | Impact |
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Added a chapter on the programming model for Root Ports to the Intel® Stratix® 10 Avalon® -MM Interface for PCI Express* Solutions User Guide. | Added the programming model for Root Ports to help users enable Root Ports. The model:
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Removed the note stating that Root Port mode is not recommended from the Intel® Stratix® 10 Avalon® -MM and Intel® Stratix® 10 Avalon® -ST for PCI Express* Solutions User Guides. | Root Port mode is fully supported in this release for both Avalon® -MM and Avalon® -ST IPs. |
Removed the BIOS Enumeration Issue section from the Troubleshooting chapter of all Intel® Stratix® 10 PCI Express* User Guides. | Since Intel® Stratix® 10 devices support the autonomous Hard IP feature, they can be recognized by the OS/BIOS during enumeration without having to be fully programmed. |
Added the note stating that the bam_response_i[1:0] inputs should be driven to 0 to the Intel® Stratix® 10 Avalon® -MM Hard IP+ for PCI Express* User Guide. | Clarified that these inputs are reserved; hence, they should be driven to 0. |
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