L/H-Tile Hard IP for PCI Express* IP Core Release Notes

ID 683412
Date 10/27/2023

1.9. L/H-Tile Hard IP for PCI Express* IP Core v18.0

Table 10.  18.0 May 2018
Description Impact
Initial release of the Avalon-MM Intel Stratix 10 Hard IP+ for PCI Express. Added a new IP component to enable Avalon® -MM support for Gen3 x16 mode. This IP core supports up to four functions. The support level is Advance.
Added support for 64-bit Avalon-MM application interface width. In addition to the native 256-bit interface available, support for a 64-bit Avalon® -MM interface (without DMA) is added.
VHDL compilation and simulation are not supported in the 18.0 release. You can only simulate and compile in Verilog in the 18.0 release.

Single Root I/O Virtualization (SR-IOV) support for H-Tile variants.

Dynamic example design generation, compilation, simulation, and hardware support for SR-IOV have been added for Avalon® -ST mode only.
First-level Signal Tap file. Support to generate a Signal Tap file through a pre-compiled script has been enabled.
Software application for the Avalon® -MM IP (with or without DMA). Linux kernel driver, API, and an example command-line application using the API are available to enable testing of the Avalon® -MM example designs (with or without DMA). The example application can also give rough estimates on the performance of the example design within the system. This application supports all link widths and speeds.
Intel® Stratix® 10 timing failures in example designs (Gen3 x16 Avalon® -ST and Gen3 x16 Avalon® -ST with SR-IOV). Small hold violations (i.e: < 5 ps slack).

Setup violations can be observed on ES devices.