AN 753: Altera JESD204B IP Core and ADI AD6676 Hardware Checkout Report

ID 683405
Date 11/02/2015

1.2. Hardware Setup

An Arria 10 GX FPGA Development Kit is used with the ADI AD6676 daughter card module installed on the development board's FMC connector.

  • For FMC port B in the Arria10 GX FPGA Development Kit, apply a jumper at pin 5-6 of J8 to set the adjustable voltage to 1.8 V.
  • The AD6676 EVM derives power from the Arria 10 FMC connector.
  • An external reference clock can be fed into the ADC EVM for the ADC device clock. To use an external reference clock, remove R95 and R100 on the AD6676 EVM.
  • Both the FPGA and ADC device clock must be sourced from the same clock source card.
  • The ADC EVM buffers the external reference clock and sends it to the FPGA as the device clock.
  • For subclass 1, the FPGA generates SYSREF for the JESD204B IP Core as well as the AD6676 device.
Figure 1. Hardware Setup

Figure 2. System-Level Block Diagram

The system-level diagram shows how different modules connect in this design.

In this setup, where LMF=222, the data rate of transceiver lanes is 4.9152 Gbps. An external reference clock of 245.76 MHz is sourced to the AD6676 EVM through the SMA. The EVM buffers the reference clock and provides the same device clock to the FPGA and AD6676. The ADC has an on-chip internal clock synthesizer that uses the reference clock to generate a 2.94912-GHz sampling clock to the converter.

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