AN 753: Altera JESD204B IP Core and ADI AD6676 Hardware Checkout Report

ID 683405
Date 11/02/2015

1.3.2. Receiver Transport Layer

To check the data integrity of the payload data stream through the RX JESD204B IP Core and transport layer, the ADC is configured to output PRBS-9 test data pattern. The ADC is also set to operate with the same configuration as set in the JESD204B IP Core. The PRBS checker in the FPGA fabric checks data integrity for one minute.

This figure shows the conceptual test setup for data integrity checking.

Figure 3. Data Integrity Check Using PRBS Checker

The SignalTap II Logic Analyzer tool monitors the operation of the RX transport layer.

Table 3.  Transport Layer Test Cases

Test Case



Passing Criteria


Check the transport layer mapping using PRBS-9 test pattern.

The following signal in is tapped:

  • jesd204_rx_data_valid

The following signals in are tapped:

  • data_error
  • jesd204_rx_int

The rxframe_clk signal is used as the SignalTap II sampling clock.

The data_error signal indicates a pass or fail for the PRBS checker.

  • The jesd204_rx_data_valid signal is asserted.
  • The data_error and jesd204_rx_int signals are deasserted.