CPRI Intel® FPGA IP Core Release Notes

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ID 683403
Date 3/01/2023
Public
Document Table of Contents
Document Table of Contents x
1. CPRI Intel® FPGA IP Core Release Notes 2. CPRI Intel® FPGA IP User Guide Archives
1. CPRI Intel® FPGA IP Core Release Notes x
1.1. CPRI Intel FPGA IP v19.6.1 1.2. CPRI Intel® FPGA IP v19.6.0 1.3. CPRI Intel® FPGA IP v19.5.0 1.4. CPRI Intel® FPGA IP v19.4.3 1.5. CPRI Intel® FPGA IP v19.4.2 1.6. CPRI Intel® FPGA IP v19.4.0 1.7. CPRI Intel® FPGA IP v19.3.0 1.8. CPRI Intel® FPGA IP v19.2.0 1.9. CPRI Intel® FPGA IP v18.1 1.10. CPRI v7.0 IP Core v17.1 1.11. CPRI v6.0 IP Core v17.0 1.12. CPRI v6.0 IP Core v14.1 1.13. CPRI v6.0 IP Core v14.0 1.14. CPRI v5.0 IP Core v13.1 1.15. CPRI v5.0 IP Core v13.0
1. CPRI Intel® FPGA IP Core Release Notes
2. CPRI Intel® FPGA IP User Guide Archives

1.11. CPRI v6.0 IP Core v17.0

Table 11.  Version 17.0 January 2018
Description Impact
Verified in the Intel® Quartus® Prime v17.0 software. —
The Intel® Stratix® 10 device support with with H- and L-tile transceivers are now available in Intel® Quartus® Prime Pro Edition v17.0 for CPRI line bit rates of 1.2288 Gbps and 10.1376 Gbps. —
Removed Intel® Arria® 10 device family support for CPRI line bit rate of 0.6144 Gbps. —
Added new parameter VCCR_GXB and VCCT_GXB supply voltage for the transceiver in Intel® Stratix® 10 IP core device variations. —
Added following new registers and signals in Intel® Stratix® 10 IP core device variations:
  • Added two new registers: XCVR_TX_FIFO_DELAY , XCVR_RX_FIFO_DELAY.
  • Added two new signals: latency_sclk, latency_sreset_n
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