CPRI Intel® FPGA IP Core Release Notes

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ID 683403
Date 3/01/2023
Public
Document Table of Contents
Document Table of Contents x
1. CPRI Intel® FPGA IP Core Release Notes 2. CPRI Intel® FPGA IP User Guide Archives
1. CPRI Intel® FPGA IP Core Release Notes x
1.1. CPRI Intel FPGA IP v19.6.1 1.2. CPRI Intel® FPGA IP v19.6.0 1.3. CPRI Intel® FPGA IP v19.5.0 1.4. CPRI Intel® FPGA IP v19.4.3 1.5. CPRI Intel® FPGA IP v19.4.2 1.6. CPRI Intel® FPGA IP v19.4.0 1.7. CPRI Intel® FPGA IP v19.3.0 1.8. CPRI Intel® FPGA IP v19.2.0 1.9. CPRI Intel® FPGA IP v18.1 1.10. CPRI v7.0 IP Core v17.1 1.11. CPRI v6.0 IP Core v17.0 1.12. CPRI v6.0 IP Core v14.1 1.13. CPRI v6.0 IP Core v14.0 1.14. CPRI v5.0 IP Core v13.1 1.15. CPRI v5.0 IP Core v13.0
1. CPRI Intel® FPGA IP Core Release Notes
2. CPRI Intel® FPGA IP User Guide Archives

1.13. CPRI v6.0 IP Core v14.0

Table 13.  Version 14.0 June 2014
Description Impact Notes
First release of the CPRI v6.0 IP core. — —
Upgraded to support the new IP Catalog. For more information about the IP Catalog, refer to IP Catalog and Parameter Editor in Introduction to Altera IP Cores. — —
Renamed Include Vendor Specific Space (VSS) access through CPU interface parameter to Include all control word access through CPU interface to better explain the function of the parameter. The parameter functionality remains as it was in the 13.1 and 13.0 releases. — —
Renamed Receiver buffer depth parameter to Receiver FIFO depth. The parameter functionality remains as it was in the 13.1 and 13.0 releases. — —
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