Interlaken (2nd Generation) Intel® FPGA IP User Guide

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ID 683396
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. Register Map 7. Test Features 8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives 9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide
1. Introduction x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Flexible Lanes Support 1.5. Round-trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA 2.6. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignment 2.6.2. Adding the External PLL 2.6.3. PMA Adaptation Flow
3. Parameter Settings x
3.1. Main Parameters 3.2. PMA Adaptation Parameters
4. Functional Description x
4.1. Interfaces 4.2. IP Clocks 4.3. High Level Data Path Flow for Interlaken Mode 4.4. High Level Data Path Flow for Interlaken Look-aside Mode 4.5. Modes of Operation 4.6. Performance 4.7. IP Core Reset 4.8. M20K ECC Support 4.9. Out-of-Band Flow Control
4.3. High Level Data Path Flow for Interlaken Mode x
4.3.1. Interlaken TX Path 4.3.2. Interlaken RX Path 4.3.3. Unused Transceiver Channels
4.3.1. Interlaken TX Path x
4.3.1.1. Transmit Path Blocks 4.3.1.2. In-Band Calendar Bits on Transmit Side
4.3.2. Interlaken RX Path x
4.3.2.1. Receive Path Blocks 4.3.2.2. In-Band Calendar Bits on Receive Side 4.3.2.3. RX Errored Packet Handling
4.3.2.3. RX Errored Packet Handling x
4.3.2.3.1. Example With Errors and In-Band Calendar Bits
4.4. High Level Data Path Flow for Interlaken Look-aside Mode x
4.4.1. Interlaken Look-aside TX Path 4.4.2. Interlaken Look-aside RX Path
4.4.1. Interlaken Look-aside TX Path x
4.4.1.1. Transmit Path Blocks
4.4.2. Interlaken Look-aside RX Path x
4.4.2.1. Receive Path Blocks 4.4.2.2. RX Error Handling
4.5. Modes of Operation x
4.5.1. Interleaved and Packet Modes 4.5.2. Interlaken Mode 4.5.3. Interlaken Look-aside Mode 4.5.4. Multi-Segment Mode
4.5.2. Interlaken Mode x
4.5.2.1. Transmit User Data Interface Examples 4.5.2.2. Receive User Data Interface Example
4.5.3. Interlaken Look-aside Mode x
4.5.3.1. Transmit User Data Interface Example 4.5.3.2. Receive User Data Interface Example
4.5.4. Multi-Segment Mode x
4.5.4.1. Multi-Segment Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals 5.7. External PLL Interface Signals
7. Test Features x
7.1. Internal Serial Loopback Mode 7.2. External Loopback Mode
1. Introduction
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. Register Map
7. Test Features
8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives
9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide

7.1. Internal Serial Loopback Mode

The Interlaken IP core supports an internal TX to RX serial loopback mode.
To turn on internal serial loopback in L- and H-tile device variations:
  • Reset the IP core by asserting and then deasserting the active low reset_n signal.
  • After reset completes, set the value of bits [NUM_LANES-1:0] of the LOOPBACK register at offset 0x12 to all ones.
    Note: Refer to IP Core Reset for information about the required wait period for register access.
  • Monitor the RX lanes aligned bit (bit 1) of the ALIGN register at offset 0x20 or the rx_lanes_aligned output signal. After the RX lanes are aligned, the IP core is in internal serial loopback mode.
To turn off internal serial loopback:
  • Reset the IP core by asserting and then deasserting the active low reset_n signal. Resetting the IP core sets the value of bits [NUM_LANES-1:0] of the LOOPBACK register at offset 0x12 to all zeros.
  • Monitor the RX lanes aligned bit (bit 0) of the ALIGN register at offset 0x20 or the rx_lanes_aligned output signal. After the RX lanes are aligned, the IP core is in normal operational mode.
To turn on internal serial loopback in E-tile device variations:
  • Reconfigure the PMA settings by using PMA attribute code 0x0008 of the transceiver PHY reconfiguration interface.
    1. Write 0x84[7:0] = 0x01
    2. Write 0x85[7:0] =0x01
    3. Write 0x86[7:0] = 0x08
    4. Write 0x87[7:0] = 0x00
    5. Write 0x90[0] = 1’b1
    6. Read 0x8A[7]. It should be 1
    7. Read 0x8B[0] until it changes to 0
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value
  • Perform the initial RX equalizer adaption calibration steps. Refer to the PMA Receiver Equalization Adaption Usage Model section in the E-Tile Transceiver PHY User Guide.
  • Reset the IP core by asserting and then deasserting the active low reset_n signal.
  • Monitor the RX lanes aligned bit (bit 1) of the ALIGN register at offset 0x20 or the rx_lanes_aligned output signal. After the RX lanes are aligned, the IP core is in internal serial loopback mode.
To turn off internal serial loopback:
  • Monitor the RX lanes aligned bit (bit 0) of the ALIGN register at offset 0x20 or the rx_lanes_aligned output signal. After the RX lanes are aligned, the IP core is in normal operational mode.
  • Reconfigure the PMA settings to turn off the serial loop back mode by using PMA attribute code 0x0008 of the transceiver PHY reconfiguration interface..
    1. Write 0x84[7:0] = 0x00
    2. Write 0x85[7:0] =0x00
    3. Write 0x86[7:0] = 0x08
    4. Write 0x87[7:0] = 0x00
    5. Write 0x90[0] = 1’b1
    6. Read 0x8A[7]. It should be 1
    7. Read 0x8B[0] until it changes to 0
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value
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