Interlaken (2nd Generation) Intel® FPGA IP User Guide

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ID 683396
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. Register Map 7. Test Features 8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives 9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide
1. Introduction x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Flexible Lanes Support 1.5. Round-trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA 2.6. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignment 2.6.2. Adding the External PLL 2.6.3. PMA Adaptation Flow
3. Parameter Settings x
3.1. Main Parameters 3.2. PMA Adaptation Parameters
4. Functional Description x
4.1. Interfaces 4.2. IP Clocks 4.3. High Level Data Path Flow for Interlaken Mode 4.4. High Level Data Path Flow for Interlaken Look-aside Mode 4.5. Modes of Operation 4.6. Performance 4.7. IP Core Reset 4.8. M20K ECC Support 4.9. Out-of-Band Flow Control
4.3. High Level Data Path Flow for Interlaken Mode x
4.3.1. Interlaken TX Path 4.3.2. Interlaken RX Path 4.3.3. Unused Transceiver Channels
4.3.1. Interlaken TX Path x
4.3.1.1. Transmit Path Blocks 4.3.1.2. In-Band Calendar Bits on Transmit Side
4.3.2. Interlaken RX Path x
4.3.2.1. Receive Path Blocks 4.3.2.2. In-Band Calendar Bits on Receive Side 4.3.2.3. RX Errored Packet Handling
4.3.2.3. RX Errored Packet Handling x
4.3.2.3.1. Example With Errors and In-Band Calendar Bits
4.4. High Level Data Path Flow for Interlaken Look-aside Mode x
4.4.1. Interlaken Look-aside TX Path 4.4.2. Interlaken Look-aside RX Path
4.4.1. Interlaken Look-aside TX Path x
4.4.1.1. Transmit Path Blocks
4.4.2. Interlaken Look-aside RX Path x
4.4.2.1. Receive Path Blocks 4.4.2.2. RX Error Handling
4.5. Modes of Operation x
4.5.1. Interleaved and Packet Modes 4.5.2. Interlaken Mode 4.5.3. Interlaken Look-aside Mode 4.5.4. Multi-Segment Mode
4.5.2. Interlaken Mode x
4.5.2.1. Transmit User Data Interface Examples 4.5.2.2. Receive User Data Interface Example
4.5.3. Interlaken Look-aside Mode x
4.5.3.1. Transmit User Data Interface Example 4.5.3.2. Receive User Data Interface Examples
4.5.4. Multi-Segment Mode x
4.5.4.1. Multi-Segment Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals 5.7. External PLL Interface Signals
7. Test Features x
7.1. Internal Serial Loopback Mode 7.2. External Loopback Mode
1. Introduction
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. Register Map
7. Test Features
8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives
9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide

2.6.3. PMA Adaptation Flow

The Interlaken (2nd Generation) Intel® FPGA IP does not start PMA adaptation in L- and H-tile device variations. If you want to enable PMA adaptation, you must start through transceiver PHY reconfiguration interface. Refer to Adaptation Control- Start section of the Intel® Stratix® 10 L- and H-tile Transceiver PHY User Guide for information on how to start PMA adaptation through transceiver PHY reconfiguration interface.

For your E-tile Interlaken IP core variations, perform the following steps to start PMA adaptation:
  1. Set the operation mode:
    • Write 0x200 = 0x1F.
    • Write 0x201 = 0x00.
    • Write 0x202 = 0x00
    • Write 0x203 = 0x93. This picks the opcode for SET_OPERATION_MODE.
    Note: Values set for 0x200 and 0x201 are just examples. Refer to Figure: Loading PMA Configuration Register SET_OPERATION_MODE in E-tile Transceiver PHY User Guide for 32-bits decoding and set it according to your design intent.
  2. Load recipe3:
    • Write 0x40143 = 0x80. Loads the PMA configuration to all channels ( 0x40143 and 0x40144 can only be accessed from channel 0).
    • Read 0x40144[0] until it reports 0x1. This ensures the process is not timed out.
  3. Start adaptation:
    • Write 0x200 = 0xF2.
    • Write 0x201 = 0x03.
    • Write 0x202 = 0x01.
    • Write 0x203 = 0x96.
    Note: Values set for 0x200, 0x201, and 0x202 are just examples. Refer to Figure: Loading PMA Configuration Register START_ADAPTATION in E-tile Transceiver PHY User Guide for 32-bits decoding and set it according to your design intent.
    Note: PRBS will not be disabled automatically after calibration if you have already enabled it in SET_OPERATION_MODE and START_ADAPTATION. You need to turn it off manually.
  4. Check ical status:
    check_stat_cal command can be run after start_cal command to return the calibration status:
    • Write 0x200 = 0x01.
    • Write 0x201 = 0x00.
    • Write 0x202 = 0x00.
    • Write 0x203 = 0x97.
    Refer to Figure: Loading PMA Configuration Register CHECK_CAL_STAT in E-tile Transceiver PHY User Guide.
  5. Poll on 0x204 and process the following status:
    • If 0x204 = 0x91, PMA adaptation in progress
    • If 0x204 = 0x80, PMA adaptation done
    • If 0x204 = 0xe2, Continuous adaptation is running
    • If 0x204 = 0xa2, One time adaptation in progress
Related Information
3 If load recipe is required.
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