Interlaken (2nd Generation) Intel® FPGA IP User Guide

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ID 683396
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. Register Map 7. Test Features 8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives 9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide
1. Introduction x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Flexible Lanes Support 1.5. Round-trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA 2.6. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignment 2.6.2. Adding the External PLL 2.6.3. PMA Adaptation Flow
3. Parameter Settings x
3.1. Main Parameters 3.2. PMA Adaptation Parameters
4. Functional Description x
4.1. Interfaces 4.2. IP Clocks 4.3. High Level Data Path Flow for Interlaken Mode 4.4. High Level Data Path Flow for Interlaken Look-aside Mode 4.5. Modes of Operation 4.6. Performance 4.7. IP Core Reset 4.8. M20K ECC Support 4.9. Out-of-Band Flow Control
4.3. High Level Data Path Flow for Interlaken Mode x
4.3.1. Interlaken TX Path 4.3.2. Interlaken RX Path 4.3.3. Unused Transceiver Channels
4.3.1. Interlaken TX Path x
4.3.1.1. Transmit Path Blocks 4.3.1.2. In-Band Calendar Bits on Transmit Side
4.3.2. Interlaken RX Path x
4.3.2.1. Receive Path Blocks 4.3.2.2. In-Band Calendar Bits on Receive Side 4.3.2.3. RX Errored Packet Handling
4.3.2.3. RX Errored Packet Handling x
4.3.2.3.1. Example With Errors and In-Band Calendar Bits
4.4. High Level Data Path Flow for Interlaken Look-aside Mode x
4.4.1. Interlaken Look-aside TX Path 4.4.2. Interlaken Look-aside RX Path
4.4.1. Interlaken Look-aside TX Path x
4.4.1.1. Transmit Path Blocks
4.4.2. Interlaken Look-aside RX Path x
4.4.2.1. Receive Path Blocks 4.4.2.2. RX Error Handling
4.5. Modes of Operation x
4.5.1. Interleaved and Packet Modes 4.5.2. Interlaken Mode 4.5.3. Interlaken Look-aside Mode 4.5.4. Multi-Segment Mode
4.5.2. Interlaken Mode x
4.5.2.1. Transmit User Data Interface Examples 4.5.2.2. Receive User Data Interface Example
4.5.3. Interlaken Look-aside Mode x
4.5.3.1. Transmit User Data Interface Example 4.5.3.2. Receive User Data Interface Examples
4.5.4. Multi-Segment Mode x
4.5.4.1. Multi-Segment Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals 5.7. External PLL Interface Signals
7. Test Features x
7.1. Internal Serial Loopback Mode 7.2. External Loopback Mode
1. Introduction
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. Register Map
7. Test Features
8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives
9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide

3.1. Main Parameters

You customize the Interlaken IP by specifying parameters in the IP parameter editor.
Table 13.  General
Parameter Supported Values Default Setting Description
Meta fame length 128-8192 2048

Specifies the meta frame length in 64-bit (8-byte) words. Must be a power of two.

Smaller values shorten the time to achieve lock. Larger values reduce the overhead while transferring data, after the clock data recover (CDR) circuit achieves lock.

Number of lanes 4, 6, 8, 10, 12 12 This parameter specifies the number of lanes available for Interlaken communication.

The Interlaken IP supports various combinations of number of lanes and lane rates. Ensure that your parameter settings specify a supported combination. Refer to Table: IP Supported Combinations of Number of Lanes and Data Rate in this document.

Data rate 6.25, 10.3125, 12.5, 25.28, 25.78, 25.78125, and 26.56254 Gbps 10.3125 Gbps This parameter specifies the data rate on each lane.

The Interlaken IP supports various combinations of number of lanes and lane rates. Ensure that your parameter settings specify a supported combination. Refer to Table: IP Supported Combinations of Number of Lanes and Data Rate in this document.

Transceiver reference clock frequency Multiple 412.5 MHz This parameter specifies the expected frequency of the pll_ref_clk input clock.

If the actual frequency of the pll_ref_clk input clock does not match the value you specify for this parameter, the design fails in both simulation and hardware.

Per-Lane Data Rate (Gbps) Valid Frequencies (MHz)
6.25 156.25, 195.3125, 250, 312.5, 390.625, 480.769236, 500 5, 6255
10.3125 156.25, 206.25, 257.8125, 322.265625, 412.5, 491.0714286, 515.6255, 644.531255
12.5 156.25, 195.3125, 250, 312.5, 390.625, 500, 6255
25.28 126.45, 158.0, 197.5, 252.8, 320.05, 395.0, 486.153846 6, 505.65
25.78 159.135802, 201.40625, 250.2912625, 322.25, 402.8125, 495.7692316, 500.5825245
25.78125 159.1435195, 159.1435186, 201.4160165, 201.4160156, 250.3033985, 322.265625, 402.832031, 500.6067965, 495.7932696
26.56257 156.25, 210.813492, 312.5, 390.625, 491.898148
Enable Interlaken Look-aside mode On/Off Off Enable this option to configure the IP core in Interlaken Look-aside mode. This option is only available in E-tile device variations.
Note: This mode is only supported in non-striper mode.
Enable M20K ECC support On/Off Off This parameter specifies whether your Interlaken IP variation supports the ECC feature in the M20K memory blocks that are configured as part of the IP.

You can turn this parameter on to enable single-error correct, double-adjacent-error correct, and triple-adjacent-error detect ECC functionality in the M20K memory blocks configured in your IP. This feature enhances data reliability but increases latency and resource utilization.

The IP does not include M20K ECC support when you turn on Enable Interlaken Look-aside option.

Enable Native PHY Debug Master Endpoint (NPDME) On/Off Off This parameter specifies whether your Interlaken IP variation supports the NPDME feature.

This parameter exposes debugging features of the Intel® Stratix® 10 Native PHY IP that specifies the transceiver settings in the Interlaken IP.

Table 14.  In-Band Flow ControlThe parameters in table below are not available when you turn on Enable Interlaken Look-aside mode parameter.
Parameter Supported Values Default Setting Description
Include in-band flow control functionality On/Off Off This parameter specifies whether your Interlaken IP includes an in-band flow control block.
Number of calender pages 1, 2, 4, 8, 16 1 This parameter specifies the number of 16-bit pages of in-band flow control data that your Interlaken IP supports. This parameter is available if you turn on Include in-band flow control functionality.

Each 16-bit calendar page includes 16 in-band flow control bits. The application determines the interpretation of the in-band flow control bits. The IP supports a maximum of 256 channels with in-band flow control.

If your design requires a different number of pages, select the lowest supported number of pages which is larger than the number required, and ignore any unused pages. For example, if your configuration requires three in-band flow control calendar pages, you can set this parameter to 4 and use pages 3, 2, and 1 while ignoring page 0.
Table 15.  Transceiver Settings
Transceiver Settings Parameter Supported Values Default Setting Description
Transceiver tile L-tile, H-tile, E-tile

H-tile

Specifies the transceiver tile on your target Intel® Stratix® 10 device. The Device setting of the Intel® Quartus® Prime Pro Edition project in which you generate the IP determines the transceiver tile type.

This parameter is not available in Intel® Agilex™ device variations. The software selects E-tile by default for Intel® Agilex™ device variations.

TX scrambler seed — 0x3ab1278890105cd

This parameter specifies the initial scrambler state. If you configure a single Interlaken IP on your device, you can use the default value of this parameter.

If you configure multiple Interlaken IPs, you must use a different initial scrambler state for each IP to reduce crosstalk. Select random values for each Interlaken IP. Each scrambler seed should have an approximately even mix of ones and zeros. The scrambler seeds should differ from the other scramblers in multiple spread out bit positions.

Transceiver mode NRZ, PAM4 NRZ Specifies the transceiver mode. This parameter is available only in IP variations that target an Intel® Stratix® 10 E-tile device.
Preserve unused transceiver channels for PAM4 On/Off Off This option can be used to preserve the unused PAM4 slave channel.8

This parameter is only available in E-tile PAM4 mode IP variations.
Reference clock frequency for preserved channels 125 MHz to 500 MHz 156 MHz When you enable Preserve unused transceiver channels for PAM4, an additional reference clock port is added to preserve the unused PAM4 slave channel. Use this parameter to set the frequency of reference clock.
VCCR_GXB and VCCT_GXB supply voltage for the transceivers 1_0V, 1_1V 1_0V This parameter specifies the VCCR_GXB and VCCT_GXB transceiver supply voltage.

Set this parameter value to 1.1V for 25.28 and 25.78 Gbps data rate. This parameter is not available in IP variations that target an Intel® Stratix® 10 and Intel® Agilex™ E-tile device.

Table 16.  User Data Transfer Interface
Parameter Supported Values Default Setting Description
Number of Segments 1, 2, 4 1 This parameter enables 1, 2, or 4 segments depending on the total number of words.

This parameter is grayed out when you turn on Enable Interlaken Look-aside mode parameter.

Related Information
4 This data rate is only available when you select PAM4 option for Transceiver Mode parameter in E-tile variations.
5 Only available in H-tile and L-tile device variations.
6 Only available in NRZ E-tile device variations.
7 Only available in PAM4 E-tile device variations.
8 For more details, refer to Unused Transceiver Channels in High-Speed PAM4 Mode.
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