Intel Agilex® 7 SoC FPGA Boot User Guide

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ID 683389
Date 2/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. FPGA Configuration First Mode 3. HPS Boot First Mode 4. Creating the Configuration Files 5. Golden System Reference Design and Design Examples 6. Configuring the FPGA Fabric from HPS Software 7. Debugging the Intel Agilex® 7 SoC FPGA Boot Flow 8. SoC FPGA Boot User Guide Archives 9. Document Revision History for Intel Agilex® 7 SoC FPGA Boot User Guide A. Boot Scratch Registers
1. Introduction x
1.1. Glossary 1.2. Intel Agilex® 7 SoC FPGA Boot Overview
2. FPGA Configuration First Mode x
2.1. Boot Flow Overview for FPGA Configuration First Mode 2.2. System Layout for FPGA Configuration First Mode
2.1. Boot Flow Overview for FPGA Configuration First Mode x
2.1.1. Power-On Reset (POR) 2.1.2. Secure Device Manager 2.1.3. First-Stage Bootloader 2.1.4. Second-Stage Bootloader 2.1.5. Operating System 2.1.63.1.6. Application2.1.63.1.6. Application
2.2. System Layout for FPGA Configuration First Mode x
2.2.1. External Configuration Host Only 2.2.2. External Configuration Host with HPS Flash 2.2.3. Single SDM Flash 2.2.4. FPGA Configuration - First Dual Flash System
3. HPS Boot First Mode x
3.1. Boot Flow Overview 3.2. System Layout for HPS Boot First Mode
3.1. Boot Flow Overview x
3.1.1. Power-On Reset (POR) 3.1.2. Secure Device Manager 3.1.3. First-Stage Bootloader 3.1.4. Second-Stage Bootloader 3.1.5. Operating System 2.1.63.1.6. Application2.1.63.1.6. Application
3.2. System Layout for HPS Boot First Mode x
3.2.1. External Configuration Host Only 3.2.2. External Configuration Host with HPS Flash 3.2.3. Single SDM Flash 3.2.4. HPS Boot First - Dual Flash System
4. Creating the Configuration Files x
4.1. Overview 4.2. Intel® Quartus® Prime Hardware Project Compilation 4.3. Bootloader Software Compilation 4.4. Programming File Generator 4.5. Configuration over JTAG 4.6. Configuration from QSPI 4.7. Configuration over AVST 4.8. Configuration via Protocol 4.9. Remote System Update 4.10. Partial Reconfiguration
4.2. Intel® Quartus® Prime Hardware Project Compilation x
4.2.1. Device and Pin Options 4.2.2. Platform Designer Options
4.5. Configuration over JTAG x
4.5.1. FPGA Configuration First 4.5.2. HPS Boots First
4.6. Configuration from QSPI x
4.6.1. Supported QSPI Devices 4.6.2. FPGA Configuration First 4.6.3. HPS Boot First
4.6.2. FPGA Configuration First x
4.6.2.1. Creating Configuration Files from Command Line 4.6.2.2. Creating Configuration Files Using Graphical Interface
4.6.3. HPS Boot First x
4.6.3.1. Creating Configuration Files from Command Line 4.6.3.2. Creating Configuration Files Using Graphical Interface
4.7. Configuration over AVST x
4.7.1. FPGA Configuration First 4.7.2. HPS Boot First
4.7.1. FPGA Configuration First x
4.7.1.1. Creating Configuration Files from Command Line 4.7.1.2. Creating Configuration Files Using Graphical Interface
4.7.2. HPS Boot First x
4.7.2.1. Creating Configuration Files from Command Line 4.7.2.2. Creating Configuration Files Using Graphical Interface
4.8. Configuration via Protocol x
4.8.1. Creating Configuration Files from Command Line 4.8.2. Creating Configuration Files Using Graphical Interface
5. Golden System Reference Design and Design Examples x
5.1. Golden System Reference Design 5.2. Bootloader Examples 5.3. Additional Design Examples
6. Configuring the FPGA Fabric from HPS Software x
6.1. Configuring the FPGA Fabric from U-Boot 6.2. Configuring the FPGA Fabric from Linux 6.3. FPGA Partial Reconfiguration from Linux
7. Debugging the Intel Agilex® 7 SoC FPGA Boot Flow x
7.1. Reset 7.2. Debugging the HPS Bootloader Using the Arm* DS* Intel® SoC FPGA Edition 7.3. Other Debug Considerations
7.1. Reset x
7.1.1. HPS Reset Pin 7.1.2. L4 Watchdog Timer 0
A. Boot Scratch Registers x
A.1. BOOT_SCRATCH_COLD0 A.2. BOOT_SCRATCH_COLD1 A.3. BOOT_SCRATCH_COLD2 A.4. BOOT_SCRATCH_COLD3 A.5. BOOT_SCRATCH_COLD4, BOOT_SCRATCH_COLD5 A.6. BOOT_SCRATCH_COLD6, BOOT_SCRATCH_COLD7 A.7. BOOT_SCRATCH_COLD8 A.8. BOOT_SCRATCH_COLD9 A.9. BOOT_SCRATCH_COLD0, BOOT_SCRATCH_COLD1, BOOT_SCRATCH_COLD8, BOOT_SCRATCH_COLD9
1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. Golden System Reference Design and Design Examples
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Intel Agilex® 7 SoC FPGA Boot Flow
8. SoC FPGA Boot User Guide Archives
9. Document Revision History for Intel Agilex® 7 SoC FPGA Boot User Guide
A. Boot Scratch Registers

A.7. BOOT_SCRATCH_COLD8

Boot Scratch Register Intel Agilex® 7 F/I-Series Intel Agilex® 7 M-Series
Boot_Scratch_Cold8
Bit[31] Can be used as scratch memory. DBE Triggered Flag
  • Values
    • 0 – DDR DBE not triggered
    • 1 – DDR DBE triggered
  • Usage
    • U-Boot
      • drivers/ddr/altera/sdram_agilex7.c: ddr_ecc_dbe_status(): Evaluates if ECC DDR DBE was triggered or not.
Bit[30] Can be used as scratch memory. DDR Init in progress, set and checked by SPL
  • Values
    • 0 – DDR initialization not performed, or completed successfully
    • 1 – DDR initialization in progress
  • Usage
    • U-Boot
      • drivers/ddr/altera/sdram_agilex7.c: is_ddr_init_hang(): checks if the bit is set
      • drivers/ddr/altera/sdram_agilex7.c: ddr_init_inprogress(): sets or clears the bit
Bit[29] Can be used as scratch memory. OCRAM_DBE Error Flag
  • Values
    • 0 – Error did not happen
    • 1 – Error happened
  • Usage
    • U-Boot
      • drivers/ddr/altera/sdram_agilex7.c hps_ocram_dbe_status(): Return the status of OCRAM DBE errors.
      • drivers/ddr/altera/sdram_agilex7.c: ddr_init_inprogress(): sets or clears the bit
Bits[28:27] Can be used as scratch memory. Number of IO96B instance assigned to HPS
  • Usage
    • U-Boot
      • drivers/ddr/altera/sdram_agilex7.c: update_io96b_assigned_to_hps(): Write the IO96B instance assigned to the HPS during DDR handoff data population.
Bit[19]
Flag to indicate a CPU power domain is about to be turned on (value = 1)
  • Usage
    • ATF:
      • plat/intel/soc/common/socfpga_psci.c: socfpga_pwr_domain_on() - Handler called when a power domain is about to be turned on.
Bit[18]
ACF DDR Data rate set by SDM
  • Values
    • 0 – Half-rate
    • 1 – Quarter-rate
  • Usage
    • U-Boot
      • drivers/ddr/altera/sdram_agilex.c: sdram_mmr_init_full(): Use the value set by SDM is scratch register to configure this in DDRIOCTRL register.
Can be used as scratch memory.
Bits[17, 16, 1]
ECC_DBE_DDR1 Error Flag, Bit[16] – ECC_DBE_DDR0 Error Flag, Bit[1] – ECC_DBE_OCRAM Error Flag
  • Values
    • 0 – Error did not happen
    • 1 – Error happened
  • Usage
    • ATF
      • plat/intel/soc/common/sip/socfpga_sip_ecc.c: cold_reset_for_ecc_dbe(): checks if any of the flags are set, and if so requests HPS cold reset through the mailbox.
    • Linux
      • Set through the ATF SMC handler
Level Two Title