F-Tile Avalon® Streaming IP for PCI Express* Design Example User Guide

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ID 683372
Date 10/20/2025
Public
Document Table of Contents
Document Table of Contents x
1. Acronyms 2. Design Example Description 3. Quick Start Guide 4. F-Tile Avalon Streaming IP for PCI Express Design Example User Guide Archives 5. Revision History for the F-Tile Avalon® Streaming IP for PCI Express* Design Example User Guide
2. Design Example Description x
2.1. Programmed Input/Output Design Example 2.2. Single Root I/O Virtualization (SR-IOV) Design Example 2.3. Performance Design Example
2.1. Programmed Input/Output Design Example x
2.1.1. Programmed Input/Output Design Example Functional Description 2.1.2. Programmed Input/Output Design Example Limitation 2.1.3. Programmed Input/Output Design Example Simulation Testbench
2.1.1. Programmed Input/Output Design Example Functional Description x
2.1.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.1.1.2. PIO Design Example for PCI Express G4 2.1.1.3. On-Chip Memory (MEM) 2.1.1.4. F-Tile Reference and System PLL Clocks IP 2.1.1.5. Reset Release IP
2.1.1.2. PIO Design Example for PCI Express G4 x
2.1.1.2.1. Scheduler 2.1.1.2.2. Read Write Module 2.1.1.2.3. Avalon-MM Interface 2.1.1.2.4. Completion Module 2.1.1.2.5. Width Adapter
2.2. Single Root I/O Virtualization (SR-IOV) Design Example x
2.2.1. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description 2.2.2. SR-IOV Design Example Limitation 2.2.3. Single Root I/O Virtualization (SR-IOV) Design Example Simulation Testbench
2.2.1. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description x
2.2.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.2.1.2. F-Tile Avalon-ST SR-IOV Example Design
2.2.1.2. F-Tile Avalon-ST SR-IOV Example Design x
2.2.1.2.1. Access Parser 2.2.1.2.2. Access Router 2.2.1.2.3. Completion 2.2.1.2.4. PF Segram 2.2.1.2.5. VF Segram 2.2.1.2.6. F-Tile Reference and System PLL Clocks IP 2.2.1.2.7. Reset Release IP
2.3. Performance Design Example x
2.3.1. Performance Design Example Functional Description 2.3.2. Performance Design Example Simulation Testbench
3. Quick Start Guide x
3.1. Directory Structure 3.2. Generating the Design Example 3.3. Simulating the Design Example 3.4. Compiling the Design Example 3.5. Hardware and Software Requirements 3.6. Program the FPGA 3.7. Installing the Linux Kernel Driver 3.8. Running the Design Example
3.3. Simulating the Design Example x
3.3.1. Steps to Run Simulation 3.3.2. Testbench
3.3.1. Steps to Run Simulation x
3.3.1.1. Steps to Run Simulation : VCS* 3.3.1.2. Steps to Run Simulation : VCS* MX 3.3.1.3. Steps to Run Simulation : Questa* 3.3.1.4. Steps to Run Simulation : Xcelium* 3.3.1.5. Steps to Run Simulation : Riviera-PRO*
3.3.2. Testbench x
3.3.2.1. Test Driver Module 3.3.2.2. PIO Design Example Testbench 3.3.2.3. SR-IOV Design Example Testbench 3.3.2.4. Performance Design Example Testbench
3.3.2.2. PIO Design Example Testbench x
3.3.2.2.1. Configure the Testbench to Perform a Dword Address-Aligned Read and Write Operation
3.8. Running the Design Example x
3.8.1. Running the PIO Design Example 3.8.2. Running the SR-IOV Design Example 3.8.3. Running the Performance Design Example
1. Acronyms
2. Design Example Description
3. Quick Start Guide
4. F-Tile Avalon Streaming IP for PCI Express Design Example User Guide Archives
5. Revision History for the F-Tile Avalon® Streaming IP for PCI Express* Design Example User Guide

3.2. Generating the Design Example

Figure 18. Procedure
  1. In the Quartus® Prime Pro Edition software, create a new project (File > New Project Wizard). Click Next.
  2. Select the Empty Project type and specify the Directory, Name, and Top-Level Entity. Click Next.
  3. For Family, Device & Board Settings under Family, select Agilex™ 7 and then select Target device for your design. After that, click Finish to proceed.
  4. Select Tools → IP Catalog to open the IP Catalog. Select the F-Tile Avalon® Streaming IP for PCI Express* (Library → Interface Protocols → PCI Express → F-Tile Avalon® Streaming IP for PCI Express* ), then click Add.
  5. In the New IP Variant dialogue box, specify a top-level name for your new custom IP variant and the directory for it. The IP Parameter Editor saves the IP variant settings in a file named <your_ip>.ip.
  6. Click Create. The IP Parameter Editor appears as shown in the figure below. The F-Tile Avalon Streaming IP for PCI Express has Top-Level Settings, PCIe0 Settings, Example Designs, and Analog Parameters tabs to allow you to quickly configure your custom IP variant.
  7. On the Top-Level Settings tabs, specify the parameters for your IP variant.
    Note: This design example only supports the default settings in the Parameter Editor of the F-tile Avalon® Streaming IP for PCIe.
    If you are using the SR-IOV design example, run the following steps to enable SR-IOV:
    1. At the PCIe Settings → PCIe PCI Express / PCI Capabilities → PCIe Device → PCIe Multifunction and SR-IOV System Settings tab, check the box Enable multiple physical functions and the Enable SR-IOV support option.
    2. At the PCIe MSI-X tab under the PCIe PCI Express / PCI Capabilities tab, enable the MSI-X feature as required.
    3. At the PCIe Base Address Registers tab under the PCIe Settings tab, enable BAR0 for both PF and VF.
    4. Other parameter settings are not supported for this design example.
  8. On the Example Designs tab, make the following selections:
    1. For Example Design Files, turn on the Simulation and Synthesis options. If you do not need these simulation or synthesis files, leaving the corresponding option(s) turned off significantly reduces the example design generation time.
    2. For Generated HDL Format, only Verilog is available in the current release.
    3. For Target Development Kit, select either the Intel Agilex 7 FPGA F-Series Development Kit (Production 1 2x F-Tile), or NONE to target on the device selected for the current Quartus Prime project. If you select the development kit, the VID-related settings including the pin assignments are included in the .qsf file of the generated design example, and you are not required to add them manually. Note that these settings are board-specific.
    4. For Device Initialization Clock, select OSC_CLK_1_125MHz when the Agilex 7 FPGA F-Series Development Kit (Production 1 2x F-Tile) is selected. Otherwise, the selected frequency must match the frequency you have provided for the device's OSC_CLK_1 pin of your board.
      Note: Starting with the Quartus® Prime Pro Edition software version 23.4, the software enforces a check for the appropriate .qsf assignment required to constrain the device’s OSC_CLK_1 pin for projects which contain transceivers in the design. A failure to provide this .qsf assignment causes the compilation to fail.
    5. For Currently Selected Example Design, select PIO/SRIOV or PERFORMANCE_DESIGN.
  9. Click on Generate Example Design to generate the design example variant. When the prompt asks you to specify the directory for your design example, you can accept the default directory, /pcie_avst_f_0_example_design, or choose another directory. Then, click OK to kick off the design example generation.
    Figure 19. Example Designs Tab
  10. Click Finish. You may save your .ip file when prompted, but it is not required to be able to use the design example.
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