F-Tile Avalon® Streaming IP for PCI Express* Design Example User Guide

Download PDF
ID 683372
Date 10/20/2025
Public
Document Table of Contents
Document Table of Contents x
1. Acronyms 2. Design Example Description 3. Quick Start Guide 4. F-Tile Avalon Streaming IP for PCI Express Design Example User Guide Archives 5. Revision History for the F-Tile Avalon® Streaming IP for PCI Express* Design Example User Guide
2. Design Example Description x
2.1. Programmed Input/Output Design Example 2.2. Single Root I/O Virtualization (SR-IOV) Design Example 2.3. Performance Design Example
2.1. Programmed Input/Output Design Example x
2.1.1. Programmed Input/Output Design Example Functional Description 2.1.2. Programmed Input/Output Design Example Limitation 2.1.3. Programmed Input/Output Design Example Simulation Testbench
2.1.1. Programmed Input/Output Design Example Functional Description x
2.1.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.1.1.2. PIO Design Example for PCI Express G4 2.1.1.3. On-Chip Memory (MEM) 2.1.1.4. F-Tile Reference and System PLL Clocks IP 2.1.1.5. Reset Release IP
2.1.1.2. PIO Design Example for PCI Express G4 x
2.1.1.2.1. Scheduler 2.1.1.2.2. Read Write Module 2.1.1.2.3. Avalon-MM Interface 2.1.1.2.4. Completion Module 2.1.1.2.5. Width Adapter
2.2. Single Root I/O Virtualization (SR-IOV) Design Example x
2.2.1. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description 2.2.2. SR-IOV Design Example Limitation 2.2.3. Single Root I/O Virtualization (SR-IOV) Design Example Simulation Testbench
2.2.1. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description x
2.2.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.2.1.2. F-Tile Avalon-ST SR-IOV Example Design
2.2.1.2. F-Tile Avalon-ST SR-IOV Example Design x
2.2.1.2.1. Access Parser 2.2.1.2.2. Access Router 2.2.1.2.3. Completion 2.2.1.2.4. PF Segram 2.2.1.2.5. VF Segram 2.2.1.2.6. F-Tile Reference and System PLL Clocks IP 2.2.1.2.7. Reset Release IP
2.3. Performance Design Example x
2.3.1. Performance Design Example Functional Description 2.3.2. Performance Design Example Simulation Testbench
3. Quick Start Guide x
3.1. Directory Structure 3.2. Generating the Design Example 3.3. Simulating the Design Example 3.4. Compiling the Design Example 3.5. Hardware and Software Requirements 3.6. Program the FPGA 3.7. Installing the Linux Kernel Driver 3.8. Running the Design Example
3.3. Simulating the Design Example x
3.3.1. Steps to Run Simulation 3.3.2. Testbench
3.3.1. Steps to Run Simulation x
3.3.1.1. Steps to Run Simulation : VCS* 3.3.1.2. Steps to Run Simulation : VCS* MX 3.3.1.3. Steps to Run Simulation : Questa* 3.3.1.4. Steps to Run Simulation : Xcelium* 3.3.1.5. Steps to Run Simulation : Riviera-PRO*
3.3.2. Testbench x
3.3.2.1. Test Driver Module 3.3.2.2. PIO Design Example Testbench 3.3.2.3. SR-IOV Design Example Testbench 3.3.2.4. Performance Design Example Testbench
3.3.2.2. PIO Design Example Testbench x
3.3.2.2.1. Configure the Testbench to Perform a Dword Address-Aligned Read and Write Operation
3.8. Running the Design Example x
3.8.1. Running the PIO Design Example 3.8.2. Running the SR-IOV Design Example 3.8.3. Running the Performance Design Example
1. Acronyms
2. Design Example Description
3. Quick Start Guide
4. F-Tile Avalon Streaming IP for PCI Express Design Example User Guide Archives
5. Revision History for the F-Tile Avalon® Streaming IP for PCI Express* Design Example User Guide

3.6. Program the FPGA

Prerequisite: Generate and compile the example design in the Quartus® Prime Pro Edition software before starting to test the design example on hardware.

This section describes how to configure the Agilex™ 7 F-Series F-Tile FPGA Development Kit.

  1. Install the Agilex™ 7 F-Series F-Tile FPGA Development Kit into a PCIe Gen4 x16 slot on the host system, connect the ATX 6-pins power supply.
  2. Connect the Agilex™ 7 F-Series F-Tile FPGA Development Kit to a computer system on which the Quartus® Prime Pro Edition software is installed using the USB cable shipped along with the development kit for FPGA configuration.
  3. Power on the host system and turn on the power switch on the development kit.
  4. In the Quartus® Prime Pro Edition software, invoke the programmer by clicking Tools > Programmer.
  5. In the Programmer, click Hardware Setup and verify the Agilex™ 7 F-Series F-Tile FPGA Development Kit is detected in the Hardware Settings tab.
    Figure 26. Hardware Settings
  6. For Currently selected hardware, select the Agilex™ 7 F-Series F-Tile FPGA Development Kit and then click Close.
  7. Click Auto Detect to detect the JTAG device chain.
  8. Select the target FPGA device in the JTAG chain, click Change File, and select the FPGA configuration file, pcie_ed.sof. Then, click Open.
  9. Check the Program/Configure option, and click Start to start the FPGA configuration.
  10. Perform a warm reboot for the host system once the Agilex™ 7 FPGA is successfully configured.
  11. Check the enumeration of the PCIe Endpoint device ( Agilex™ 7 F-Series F-Tile FPGA Development Kit) on the host system by running the “lspci –d 1172:” command in a Linux Terminal.

    Expected result:

    BDF Unassigned class [ff00]: Altera Corporation Device 0000 (rev 01)

Level Two Title