F-Tile Avalon® Streaming IP for PCI Express* Design Example User Guide

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ID 683372
Date 10/20/2025
Public
Document Table of Contents
Document Table of Contents x
1. Acronyms 2. Design Example Description 3. Quick Start Guide 4. F-Tile Avalon Streaming IP for PCI Express Design Example User Guide Archives 5. Revision History for the F-Tile Avalon® Streaming IP for PCI Express* Design Example User Guide
2. Design Example Description x
2.1. Programmed Input/Output Design Example 2.2. Single Root I/O Virtualization (SR-IOV) Design Example 2.3. Performance Design Example
2.1. Programmed Input/Output Design Example x
2.1.1. Programmed Input/Output Design Example Functional Description 2.1.2. Programmed Input/Output Design Example Limitation 2.1.3. Programmed Input/Output Design Example Simulation Testbench
2.1.1. Programmed Input/Output Design Example Functional Description x
2.1.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.1.1.2. PIO Design Example for PCI Express G4 2.1.1.3. On-Chip Memory (MEM) 2.1.1.4. F-Tile Reference and System PLL Clocks IP 2.1.1.5. Reset Release IP
2.1.1.2. PIO Design Example for PCI Express G4 x
2.1.1.2.1. Scheduler 2.1.1.2.2. Read Write Module 2.1.1.2.3. Avalon-MM Interface 2.1.1.2.4. Completion Module 2.1.1.2.5. Width Adapter
2.2. Single Root I/O Virtualization (SR-IOV) Design Example x
2.2.1. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description 2.2.2. SR-IOV Design Example Limitation 2.2.3. Single Root I/O Virtualization (SR-IOV) Design Example Simulation Testbench
2.2.1. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description x
2.2.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.2.1.2. F-Tile Avalon-ST SR-IOV Example Design
2.2.1.2. F-Tile Avalon-ST SR-IOV Example Design x
2.2.1.2.1. Access Parser 2.2.1.2.2. Access Router 2.2.1.2.3. Completion 2.2.1.2.4. PF Segram 2.2.1.2.5. VF Segram 2.2.1.2.6. F-Tile Reference and System PLL Clocks IP 2.2.1.2.7. Reset Release IP
2.3. Performance Design Example x
2.3.1. Performance Design Example Functional Description 2.3.2. Performance Design Example Simulation Testbench
3. Quick Start Guide x
3.1. Directory Structure 3.2. Generating the Design Example 3.3. Simulating the Design Example 3.4. Compiling the Design Example 3.5. Hardware and Software Requirements 3.6. Program the FPGA 3.7. Installing the Linux Kernel Driver 3.8. Running the Design Example
3.3. Simulating the Design Example x
3.3.1. Steps to Run Simulation 3.3.2. Testbench
3.3.1. Steps to Run Simulation x
3.3.1.1. Steps to Run Simulation : VCS* 3.3.1.2. Steps to Run Simulation : VCS* MX 3.3.1.3. Steps to Run Simulation : Questa* 3.3.1.4. Steps to Run Simulation : Xcelium* 3.3.1.5. Steps to Run Simulation : Riviera-PRO*
3.3.2. Testbench x
3.3.2.1. Test Driver Module 3.3.2.2. PIO Design Example Testbench 3.3.2.3. SR-IOV Design Example Testbench 3.3.2.4. Performance Design Example Testbench
3.3.2.2. PIO Design Example Testbench x
3.3.2.2.1. Configure the Testbench to Perform a Dword Address-Aligned Read and Write Operation
3.8. Running the Design Example x
3.8.1. Running the PIO Design Example 3.8.2. Running the SR-IOV Design Example 3.8.3. Running the Performance Design Example
1. Acronyms
2. Design Example Description
3. Quick Start Guide
4. F-Tile Avalon Streaming IP for PCI Express Design Example User Guide Archives
5. Revision History for the F-Tile Avalon® Streaming IP for PCI Express* Design Example User Guide

3.3.2.2.1. Configure the Testbench to Perform a Dword Address-Aligned Read and Write Operation

The simulation testbench from the Programmed Input/Output (PIO) design example can be modified to demonstrate Double Word (DW) address alignment through 16 iterations of Memory Write (MWr) and Memory Read (MRd) operations. The initial address is set to 0x00, with a payload size of 1 DW. In each iteration, both the Transaction Layer Packet (TLP) payload and the request address increment by 1 DW. The data retrieved from MRd operations are validated against the corresponding MWr data. Any mismatches identified during the comparison are logged as errors in the simulation logfile.

Note: This is currently supported in the design example variant for the 512-bit Hard IP mode.

The waveform shows the increment of the address and payload size.

First iteration (address of 0000_0001_0000_0000, payload of 1DW)

Second iteration (address of 0000_0001_0000_0004, payload of 2DW)

  1. Locate the file altpcietb_bfm_rp_gen4_x16.sv in the <design example directory>/pcie_ed_sim_tb/ip/pcie_ed_sim_tb/dut_pcie_tb_ip/intel_pcie_ftile_tbed_100/sim/ directory.
  2. Modify the following localparam in the altpcietb_bfm_rp_gen4_x16.sv file as shown below:

    Line 6037: RCSLAVE_MAXLEN=16;

    Note: The RCSLAVE_MAXLEN is to control the loop count of the MWr/MRd instruction routines.
  3. Task downstream_read is responsible for the MWr/MRd instruction routines. It initiates the MWr and MRd based on the variable passed in.
    1. Insert “Iepmem_address = epmem_address;” after line 7407.
    2. Comment out “Ibyte_length=4; at line 7411.
    3. Rename lines 7414 and 7421 from “epmem_address;” to “Iepmem_address,”.
    4. Uncomment line 7424 to enable a delay of #1000000.
    5. Insert “Iepmem_address = Ibyte_length;” after line 7429.
  4. The successful run should have 16 iterations of MWr and MRd. The logfile should contain the message “successful completion!”
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