F-Tile Avalon® Streaming IP for PCI Express* Design Example User Guide

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ID 683372
Date 10/20/2025
Public
Document Table of Contents
Document Table of Contents x
1. Acronyms 2. Design Example Description 3. Quick Start Guide 4. F-Tile Avalon Streaming IP for PCI Express Design Example User Guide Archives 5. Revision History for the F-Tile Avalon® Streaming IP for PCI Express* Design Example User Guide
2. Design Example Description x
2.1. Programmed Input/Output Design Example 2.2. Single Root I/O Virtualization (SR-IOV) Design Example 2.3. Performance Design Example
2.1. Programmed Input/Output Design Example x
2.1.1. Programmed Input/Output Design Example Functional Description 2.1.2. Programmed Input/Output Design Example Limitation 2.1.3. Programmed Input/Output Design Example Simulation Testbench
2.1.1. Programmed Input/Output Design Example Functional Description x
2.1.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.1.1.2. PIO Design Example for PCI Express G4 2.1.1.3. On-Chip Memory (MEM) 2.1.1.4. F-Tile Reference and System PLL Clocks IP 2.1.1.5. Reset Release IP
2.1.1.2. PIO Design Example for PCI Express G4 x
2.1.1.2.1. Scheduler 2.1.1.2.2. Read Write Module 2.1.1.2.3. Avalon-MM Interface 2.1.1.2.4. Completion Module 2.1.1.2.5. Width Adapter
2.2. Single Root I/O Virtualization (SR-IOV) Design Example x
2.2.1. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description 2.2.2. SR-IOV Design Example Limitation 2.2.3. Single Root I/O Virtualization (SR-IOV) Design Example Simulation Testbench
2.2.1. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description x
2.2.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.2.1.2. F-Tile Avalon-ST SR-IOV Example Design
2.2.1.2. F-Tile Avalon-ST SR-IOV Example Design x
2.2.1.2.1. Access Parser 2.2.1.2.2. Access Router 2.2.1.2.3. Completion 2.2.1.2.4. PF Segram 2.2.1.2.5. VF Segram 2.2.1.2.6. F-Tile Reference and System PLL Clocks IP 2.2.1.2.7. Reset Release IP
2.3. Performance Design Example x
2.3.1. Performance Design Example Functional Description 2.3.2. Performance Design Example Simulation Testbench
3. Quick Start Guide x
3.1. Directory Structure 3.2. Generating the Design Example 3.3. Simulating the Design Example 3.4. Compiling the Design Example 3.5. Hardware and Software Requirements 3.6. Program the FPGA 3.7. Installing the Linux Kernel Driver 3.8. Running the Design Example
3.3. Simulating the Design Example x
3.3.1. Steps to Run Simulation 3.3.2. Testbench
3.3.1. Steps to Run Simulation x
3.3.1.1. Steps to Run Simulation : VCS* 3.3.1.2. Steps to Run Simulation : VCS* MX 3.3.1.3. Steps to Run Simulation : Questa* 3.3.1.4. Steps to Run Simulation : Xcelium* 3.3.1.5. Steps to Run Simulation : Riviera-PRO*
3.3.2. Testbench x
3.3.2.1. Test Driver Module 3.3.2.2. PIO Design Example Testbench 3.3.2.3. SR-IOV Design Example Testbench 3.3.2.4. Performance Design Example Testbench
3.3.2.2. PIO Design Example Testbench x
3.3.2.2.1. Configure the Testbench to Perform a Dword Address-Aligned Read and Write Operation
3.8. Running the Design Example x
3.8.1. Running the PIO Design Example 3.8.2. Running the SR-IOV Design Example 3.8.3. Running the Performance Design Example
1. Acronyms
2. Design Example Description
3. Quick Start Guide
4. F-Tile Avalon Streaming IP for PCI Express Design Example User Guide Archives
5. Revision History for the F-Tile Avalon® Streaming IP for PCI Express* Design Example User Guide

3.8.2. Running the SR-IOV Design Example

Before you can test the design example in hardware, you must enable SR-IOV and ARI (Alternative Routing ID Interpretation) in the BIOS, configure the FPGA, and then restart your computer to allow the enumeration to take place for the PCIe device. After that, install the Linux kernel driver as described in Installing the Linux Kernel Driver.

Here are the steps to test the SR-IOV design example on hardware:
  1. In the host system, navigate to the ./software/user/example directory of the software driver.
  2. Compile the design example software application by running the make command: $ make.
  3. Run the test by running the following command: $ sudo ./intel_fpga_pcie_link_test.
  4. Select Option 1: Manually Select a Device to specify the Bus-Device-Function (BDF) of the Physical Function (PF) to which the Virtual Functions (VFs) are assigned.
  5. Enter BAR “0” to proceed to the test menu.
  6. Enter option 7 to enable SR-IOV for the current device.
  7. Enter the number of virtual functions to be enabled for the current device.
    Figure 29. Link Test Menu
    Note: To disable VF for the current device, repeat Step 6: Select option 7 to enable SR-IOV, enter 0 for the number of VFs to be enabled.
    Note: Type 'lspci -d 1172:' in a new terminal to determine the BDFs of the newly enabled VFs.
  8. In a new terminal, run the 
    sudo lspci –d 1172: | grep -c “Altera”
    command to verify the enumeration of PFs and VFs. The expected result is the sum of the number of physical functions and number of virtual functions. In this example, there are 2 PFs and 32 VFs are enabled for each PF. Running this command returns 66 as shown in the figure below.
    Figure 30. lspci command
  9. Enter option 8 to perform a link test for every enabled virtual function allocated for the physical function. The link test application performs 100 memory writes with a single dword of data each and then reads the data back for checking. The application prints the number of virtual functions that failed the link test at the end of the testing.
    Figure 31. Test Result
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